Lines Matching refs:pipeline
129 bool radv_pipeline_has_ngg(const struct radv_pipeline *pipeline) in radv_pipeline_has_ngg() argument
132 if (pipeline->shaders[MESA_SHADER_GEOMETRY]) in radv_pipeline_has_ngg()
133 variant = pipeline->shaders[MESA_SHADER_GEOMETRY]; in radv_pipeline_has_ngg()
134 else if (pipeline->shaders[MESA_SHADER_TESS_EVAL]) in radv_pipeline_has_ngg()
135 variant = pipeline->shaders[MESA_SHADER_TESS_EVAL]; in radv_pipeline_has_ngg()
136 else if (pipeline->shaders[MESA_SHADER_VERTEX]) in radv_pipeline_has_ngg()
137 variant = pipeline->shaders[MESA_SHADER_VERTEX]; in radv_pipeline_has_ngg()
143 bool radv_pipeline_has_ngg_passthrough(const struct radv_pipeline *pipeline) in radv_pipeline_has_ngg_passthrough() argument
145 assert(radv_pipeline_has_ngg(pipeline)); in radv_pipeline_has_ngg_passthrough()
148 if (pipeline->shaders[MESA_SHADER_GEOMETRY]) in radv_pipeline_has_ngg_passthrough()
149 variant = pipeline->shaders[MESA_SHADER_GEOMETRY]; in radv_pipeline_has_ngg_passthrough()
150 else if (pipeline->shaders[MESA_SHADER_TESS_EVAL]) in radv_pipeline_has_ngg_passthrough()
151 variant = pipeline->shaders[MESA_SHADER_TESS_EVAL]; in radv_pipeline_has_ngg_passthrough()
152 else if (pipeline->shaders[MESA_SHADER_VERTEX]) in radv_pipeline_has_ngg_passthrough()
153 variant = pipeline->shaders[MESA_SHADER_VERTEX]; in radv_pipeline_has_ngg_passthrough()
159 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline *pipeline) in radv_pipeline_has_gs_copy_shader() argument
161 if (!radv_pipeline_has_gs(pipeline)) in radv_pipeline_has_gs_copy_shader()
168 if (radv_pipeline_has_ngg(pipeline)) in radv_pipeline_has_gs_copy_shader()
171 assert(pipeline->gs_copy_shader); in radv_pipeline_has_gs_copy_shader()
177 struct radv_pipeline *pipeline, in radv_pipeline_destroy() argument
181 if (pipeline->shaders[i]) in radv_pipeline_destroy()
182 radv_shader_variant_destroy(device, pipeline->shaders[i]); in radv_pipeline_destroy()
184 if (pipeline->gs_copy_shader) in radv_pipeline_destroy()
185 radv_shader_variant_destroy(device, pipeline->gs_copy_shader); in radv_pipeline_destroy()
187 if(pipeline->cs.buf) in radv_pipeline_destroy()
188 free(pipeline->cs.buf); in radv_pipeline_destroy()
190 vk_object_base_finish(&pipeline->base); in radv_pipeline_destroy()
191 vk_free2(&device->vk.alloc, allocator, pipeline); in radv_pipeline_destroy()
200 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline); in radv_DestroyPipeline()
205 radv_pipeline_destroy(device, pipeline, pAllocator); in radv_DestroyPipeline()
233 struct radv_pipeline *pipeline) in radv_pipeline_init_scratch() argument
240 if (pipeline->shaders[i] && in radv_pipeline_init_scratch()
241 pipeline->shaders[i]->config.scratch_bytes_per_wave) { in radv_pipeline_init_scratch()
245 pipeline->shaders[i]->config.scratch_bytes_per_wave); in radv_pipeline_init_scratch()
249 (256 / pipeline->shaders[i]->config.num_vgprs)); in radv_pipeline_init_scratch()
254 if (pipeline->shaders[MESA_SHADER_COMPUTE]) { in radv_pipeline_init_scratch()
255 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] * in radv_pipeline_init_scratch()
256 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] * in radv_pipeline_init_scratch()
257 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2]; in radv_pipeline_init_scratch()
261 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave; in radv_pipeline_init_scratch()
262 pipeline->max_waves = max_waves; in radv_pipeline_init_scratch()
506 radv_pipeline_compute_spi_color_formats(const struct radv_pipeline *pipeline, in radv_pipeline_compute_spi_color_formats() argument
639 radv_pipeline_init_blend_state(const struct radv_pipeline *pipeline, in radv_pipeline_init_blend_state() argument
795 if (pipeline->device->physical_device->rad_info.has_rbplus) { in radv_pipeline_init_blend_state()
819 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo, &blend); in radv_pipeline_init_blend_state()
963 radv_pipeline_out_of_order_rast(struct radv_pipeline *pipeline, in radv_pipeline_out_of_order_rast() argument
973 if (!pipeline->device->physical_device->out_of_order_rast_allowed) in radv_pipeline_out_of_order_rast()
998 pipeline->shaders[MESA_SHADER_FRAGMENT]; in radv_pipeline_out_of_order_rast()
1049 pipeline->graphics.disable_out_of_order_rast_for_occlusion = in radv_pipeline_out_of_order_rast()
1086 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline, in radv_pipeline_init_multisample_state() argument
1091 struct radv_multisample_state *ms = &pipeline->graphics.ms; in radv_pipeline_init_multisample_state()
1092 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes; in radv_pipeline_init_multisample_state()
1118 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.force_persample) { in radv_pipeline_init_multisample_state()
1139 radv_pipeline_out_of_order_rast(pipeline, blend, pCreateInfo); in radv_pipeline_init_multisample_state()
1168 …ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_inf… in radv_pipeline_init_multisample_state()
1203 …S_028BE0_COVERED_CENTROID_IS_CENTER(pipeline->device->physical_device->rad_info.chip_class >= GFX1… in radv_pipeline_init_multisample_state()
1206 pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2); in radv_pipeline_init_multisample_state()
1386 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline) in radv_compute_ia_multi_vgt_param_helpers() argument
1389 const struct radv_device *device = pipeline->device; in radv_compute_ia_multi_vgt_param_helpers()
1391 if (radv_pipeline_has_tess(pipeline)) in radv_compute_ia_multi_vgt_param_helpers()
1392 …ia_multi_vgt_param.primgroup_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches; in radv_compute_ia_multi_vgt_param_helpers()
1393 else if (radv_pipeline_has_gs(pipeline)) in radv_compute_ia_multi_vgt_param_helpers()
1400 if (radv_pipeline_has_gs(pipeline) && device->physical_device->rad_info.chip_class <= GFX8) in radv_compute_ia_multi_vgt_param_helpers()
1401 if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= pipeline->device->gs_table_depth - 3) in radv_compute_ia_multi_vgt_param_helpers()
1405 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.prim_id_input) in radv_compute_ia_multi_vgt_param_helpers()
1407 if (radv_pipeline_has_gs(pipeline) && in radv_compute_ia_multi_vgt_param_helpers()
1408 pipeline->shaders[MESA_SHADER_GEOMETRY]->info.uses_prim_id) in radv_compute_ia_multi_vgt_param_helpers()
1410 if (radv_pipeline_has_tess(pipeline)) { in radv_compute_ia_multi_vgt_param_helpers()
1412 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id || in radv_compute_ia_multi_vgt_param_helpers()
1413 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.uses_prim_id) in radv_compute_ia_multi_vgt_param_helpers()
1418 if (radv_pipeline_has_tess(pipeline)) { in radv_compute_ia_multi_vgt_param_helpers()
1423 radv_pipeline_has_gs(pipeline)) in radv_compute_ia_multi_vgt_param_helpers()
1427 if (radv_pipeline_has_gs(pipeline)) { in radv_compute_ia_multi_vgt_param_helpers()
1436 if (radv_pipeline_has_gs(pipeline)) { in radv_compute_ia_multi_vgt_param_helpers()
1467 radv_pipeline_init_input_assembly_state(struct radv_pipeline *pipeline, in radv_pipeline_init_input_assembly_state() argument
1472 struct radv_shader_variant *tes = pipeline->shaders[MESA_SHADER_TESS_EVAL]; in radv_pipeline_init_input_assembly_state()
1473 struct radv_shader_variant *gs = pipeline->shaders[MESA_SHADER_GEOMETRY]; in radv_pipeline_init_input_assembly_state()
1475 pipeline->graphics.prim_restart_enable = !!ia_state->primitiveRestartEnable; in radv_pipeline_init_input_assembly_state()
1476 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(ia_state->topology); in radv_pipeline_init_input_assembly_state()
1478 if (radv_pipeline_has_gs(pipeline)) { in radv_pipeline_init_input_assembly_state()
1480 pipeline->graphics.can_use_guardband = true; in radv_pipeline_init_input_assembly_state()
1481 } else if (radv_pipeline_has_tess(pipeline)) { in radv_pipeline_init_input_assembly_state()
1484 pipeline->graphics.can_use_guardband = true; in radv_pipeline_init_input_assembly_state()
1488 pipeline->graphics.can_use_guardband = true; in radv_pipeline_init_input_assembly_state()
1491 pipeline->graphics.ia_multi_vgt_param = in radv_pipeline_init_input_assembly_state()
1492 radv_compute_ia_multi_vgt_param_helpers(pipeline); in radv_pipeline_init_input_assembly_state()
1496 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline, in radv_pipeline_init_dynamic_state() argument
1505 pipeline->dynamic_state = default_dynamic_state; in radv_pipeline_init_dynamic_state()
1506 pipeline->graphics.needed_dynamic_state = needed_states; in radv_pipeline_init_dynamic_state()
1515 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state; in radv_pipeline_init_dynamic_state()
1714 pipeline->graphics.uses_dynamic_stride = true; in radv_pipeline_init_dynamic_state()
1716 pipeline->dynamic_state.mask = states; in radv_pipeline_init_dynamic_state()
1720 radv_pipeline_init_raster_state(struct radv_pipeline *pipeline, in radv_pipeline_init_raster_state() argument
1726 pipeline->graphics.pa_su_sc_mode_cntl = in radv_pipeline_init_raster_state()
1737 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) { in radv_pipeline_init_raster_state()
1739 pipeline->graphics.pa_su_sc_mode_cntl |= in radv_pipeline_init_raster_state()
1745 radv_pipeline_init_depth_stencil_state(struct radv_pipeline *pipeline, in radv_pipeline_init_depth_stencil_state() argument
1776 pipeline->graphics.db_depth_control = db_depth_control; in radv_pipeline_init_depth_stencil_state()
1781 const struct radv_pipeline *pipeline, in gfx9_get_gs_info() argument
1788 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) in gfx9_get_gs_info()
1934 struct radv_pipeline *pipeline, in gfx10_get_ngg_info() argument
1974 …const unsigned min_esverts = pipeline->device->physical_device->rad_info.chip_class >= GFX10_3 ? 2… in gfx10_get_ngg_info()
2150 pipeline->graphics.esgs_ring_size = ngg->esgs_ring_size; in gfx10_get_ngg_info()
2156 radv_pipeline_init_gs_ring_state(struct radv_pipeline *pipeline, in radv_pipeline_init_gs_ring_state() argument
2159 struct radv_device *device = pipeline->device; in radv_pipeline_init_gs_ring_state()
2171 struct radv_shader_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info; in radv_pipeline_init_gs_ring_state()
2186 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8) in radv_pipeline_init_gs_ring_state()
2187 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size); in radv_pipeline_init_gs_ring_state()
2189 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size); in radv_pipeline_init_gs_ring_state()
2193 radv_get_shader(const struct radv_pipeline *pipeline, in radv_get_shader() argument
2197 if (pipeline->shaders[MESA_SHADER_VERTEX]) in radv_get_shader()
2198 return pipeline->shaders[MESA_SHADER_VERTEX]; in radv_get_shader()
2199 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]) in radv_get_shader()
2200 return pipeline->shaders[MESA_SHADER_TESS_CTRL]; in radv_get_shader()
2201 if (pipeline->shaders[MESA_SHADER_GEOMETRY]) in radv_get_shader()
2202 return pipeline->shaders[MESA_SHADER_GEOMETRY]; in radv_get_shader()
2204 if (!radv_pipeline_has_tess(pipeline)) in radv_get_shader()
2206 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]) in radv_get_shader()
2207 return pipeline->shaders[MESA_SHADER_TESS_EVAL]; in radv_get_shader()
2208 if (pipeline->shaders[MESA_SHADER_GEOMETRY]) in radv_get_shader()
2209 return pipeline->shaders[MESA_SHADER_GEOMETRY]; in radv_get_shader()
2211 return pipeline->shaders[stage]; in radv_get_shader()
2214 static const struct radv_vs_output_info *get_vs_output_info(const struct radv_pipeline *pipeline) in get_vs_output_info() argument
2216 if (radv_pipeline_has_gs(pipeline)) in get_vs_output_info()
2217 if (radv_pipeline_has_ngg(pipeline)) in get_vs_output_info()
2218 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.vs.outinfo; in get_vs_output_info()
2220 return &pipeline->gs_copy_shader->info.vs.outinfo; in get_vs_output_info()
2221 else if (radv_pipeline_has_tess(pipeline)) in get_vs_output_info()
2222 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo; in get_vs_output_info()
2224 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo; in get_vs_output_info()
2228 radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders, in radv_link_shaders() argument
2328 pipeline->device->physical_device->rad_info.chip_class); in radv_link_shaders()
2336 pipeline->device->physical_device->rad_info.chip_class); in radv_link_shaders()
2343 radv_set_driver_locations(struct radv_pipeline *pipeline, nir_shader **shaders, in radv_set_driver_locations() argument
2362 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) { in radv_set_driver_locations()
2425 radv_generate_graphics_pipeline_key(const struct radv_pipeline *pipeline, in radv_generate_graphics_pipeline_key() argument
2516 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8 && in radv_generate_graphics_pipeline_key()
2517 pipeline->device->physical_device->rad_info.family != CHIP_STONEY) { in radv_generate_graphics_pipeline_key()
2575 if (pipeline->device->physical_device->rad_info.chip_class < GFX8) { in radv_generate_graphics_pipeline_key()
2580 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) in radv_generate_graphics_pipeline_key()
2729 radv_fill_shader_info(struct radv_pipeline *pipeline, in radv_fill_shader_info() argument
2746 pipeline->layout, in radv_fill_shader_info()
2788 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 && in radv_fill_shader_info()
2798 pipeline->layout, &key, in radv_fill_shader_info()
2809 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 && in radv_fill_shader_info()
2818 pipeline->layout, in radv_fill_shader_info()
2837 radv_nir_shader_info_pass(nir[i], pipeline->layout, in radv_fill_shader_info()
2844 radv_get_wave_size(pipeline->device, pStages[i], in radv_fill_shader_info()
2847 radv_get_ballot_bit_size(pipeline->device, in radv_fill_shader_info()
3039 VkResult radv_create_shaders(struct radv_pipeline *pipeline, in radv_create_shaders() argument
3071 pipeline->active_stages |= mesa_to_vk_shader_stage(i); in radv_create_shaders()
3075 radv_hash_shaders(hash, pStages, pipeline->layout, key, get_hash_flags(device)); in radv_create_shaders()
3084 pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY]; in radv_create_shaders()
3088 radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders, in radv_create_shaders()
3090 (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) { in radv_create_shaders()
3129 flags, pipeline->layout, in radv_create_shaders()
3149 radv_link_shaders(pipeline, nir, optimize_conservatively); in radv_create_shaders()
3159 radv_set_driver_locations(pipeline, nir, infos); in radv_create_shaders()
3277 radv_fill_shader_info(pipeline, pStages, keys, infos, nir); in radv_create_shaders()
3292 gfx10_get_ngg_info(key, pipeline, nir, infos, ngg_info); in radv_create_shaders()
3297 gfx9_get_gs_info(key, pipeline, nir, infos, gs_info); in radv_create_shaders()
3302 if (!pipeline->gs_copy_shader && in radv_create_shaders()
3303 !radv_pipeline_has_ngg(pipeline)) { in radv_create_shaders()
3311 pipeline->layout, &key, in radv_create_shaders()
3316 pipeline->gs_copy_shader = radv_create_gs_copy_shader( in radv_create_shaders()
3323 if (!keep_executable_info && !keep_statistic_info && pipeline->gs_copy_shader) { in radv_create_shaders()
3328 variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader; in radv_create_shaders()
3339 if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) { in radv_create_shaders()
3342 pipeline->shaders[MESA_SHADER_FRAGMENT] = in radv_create_shaders()
3344 pipeline->layout, keys + MESA_SHADER_FRAGMENT, in radv_create_shaders()
3355 if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) { in radv_create_shaders()
3362 …pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_compile(device, modules[MESA_SHADER… in radv_create_shaders()
3363 pipeline->layout, in radv_create_shaders()
3372 …keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.n… in radv_create_shaders()
3377 if (!pipeline->shaders[MESA_SHADER_GEOMETRY]) { in radv_create_shaders()
3382 …pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_compile(device, modules[MESA_SHADER_… in radv_create_shaders()
3383 pipeline->layout, in radv_create_shaders()
3395 if(modules[i] && !pipeline->shaders[i]) { in radv_create_shaders()
3397 …keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.n… in radv_create_shaders()
3402 pipeline->shaders[i] = radv_shader_variant_compile(device, modules[i], &nir[i], 1, in radv_create_shaders()
3403 pipeline->layout, in radv_create_shaders()
3414 radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders, in radv_create_shaders()
3424 radv_dump_shader_stats(device, pipeline, i, stderr); in radv_create_shaders()
3437 radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline, in radv_pipeline_stage_to_user_data_0() argument
3440 bool has_gs = radv_pipeline_has_gs(pipeline); in radv_pipeline_stage_to_user_data_0()
3441 bool has_tess = radv_pipeline_has_tess(pipeline); in radv_pipeline_stage_to_user_data_0()
3442 bool has_ngg = radv_pipeline_has_ngg(pipeline); in radv_pipeline_stage_to_user_data_0()
3499 radv_gfx9_compute_bin_size(const struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo… in radv_gfx9_compute_bin_size() argument
3716 util_logbase2_ceil(pipeline->device->physical_device->rad_info.num_render_backends / in radv_gfx9_compute_bin_size()
3717 pipeline->device->physical_device->rad_info.max_se); in radv_gfx9_compute_bin_size()
3718 unsigned log_num_se = util_logbase2_ceil(pipeline->device->physical_device->rad_info.max_se); in radv_gfx9_compute_bin_size()
3720 unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config); in radv_gfx9_compute_bin_size()
3721 unsigned ps_iter_samples = 1u << G_028804_PS_ITER_SAMPLES(pipeline->graphics.ms.db_eqaa); in radv_gfx9_compute_bin_size()
3771 radv_gfx10_compute_bin_size(const struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInf… in radv_gfx10_compute_bin_size() argument
3784 const unsigned rb_count = pipeline->device->physical_device->rad_info.num_render_backends; in radv_gfx10_compute_bin_size()
3785 …const unsigned pipe_count = MAX2(rb_count, pipeline->device->physical_device->rad_info.num_sdp_int… in radv_gfx10_compute_bin_size()
3791 …const unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_conf… in radv_gfx10_compute_bin_size()
3863 radv_pipeline_init_disabled_binning_state(struct radv_pipeline *pipeline, in radv_pipeline_init_disabled_binning_state() argument
3871 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) { in radv_pipeline_init_disabled_binning_state()
3902 pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0; in radv_pipeline_init_disabled_binning_state()
3903 pipeline->graphics.binning.db_dfsm_control = db_dfsm_control; in radv_pipeline_init_disabled_binning_state()
3934 radv_pipeline_init_binning_state(struct radv_pipeline *pipeline, in radv_pipeline_init_binning_state() argument
3938 if (pipeline->device->physical_device->rad_info.chip_class < GFX9) in radv_pipeline_init_binning_state()
3942 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) { in radv_pipeline_init_binning_state()
3943 bin_size = radv_gfx10_compute_bin_size(pipeline, pCreateInfo); in radv_pipeline_init_binning_state()
3944 } else if (pipeline->device->physical_device->rad_info.chip_class == GFX9) { in radv_pipeline_init_binning_state()
3945 bin_size = radv_gfx9_compute_bin_size(pipeline, pCreateInfo); in radv_pipeline_init_binning_state()
3949 if (pipeline->device->pbb_allowed && bin_size.width && bin_size.height) { in radv_pipeline_init_binning_state()
3951 radv_get_binning_settings(pipeline->device->physical_device); in radv_pipeline_init_binning_state()
3956 const struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT]; in radv_pipeline_init_binning_state()
3958 if (pipeline->device->dfsm_allowed && ps && in radv_pipeline_init_binning_state()
3978 pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0; in radv_pipeline_init_binning_state()
3979 pipeline->graphics.binning.db_dfsm_control = db_dfsm_control; in radv_pipeline_init_binning_state()
3981 radv_pipeline_init_disabled_binning_state(pipeline, pCreateInfo); in radv_pipeline_init_binning_state()
3987 const struct radv_pipeline *pipeline, in radv_pipeline_generate_depth_stencil_state() argument
3994 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT]; in radv_pipeline_generate_depth_stencil_state()
4008 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10_3) in radv_pipeline_generate_depth_stencil_state()
4048 const struct radv_pipeline *pipeline, in radv_pipeline_generate_blend_state() argument
4057 if (pipeline->device->physical_device->rad_info.has_rbplus) { in radv_pipeline_generate_blend_state()
4071 const struct radv_pipeline *pipeline, in radv_pipeline_generate_raster_state() argument
4127 const struct radv_pipeline *pipeline) in radv_pipeline_generate_multisample_state() argument
4129 const struct radv_multisample_state *ms = &pipeline->graphics.ms; in radv_pipeline_generate_multisample_state()
4144 bool exclusion = pipeline->device->physical_device->rad_info.chip_class >= GFX7; in radv_pipeline_generate_multisample_state()
4150 if (pipeline->device->dfsm_allowed) { in radv_pipeline_generate_multisample_state()
4158 const struct radv_pipeline *pipeline) in radv_pipeline_generate_vgt_gs_mode() argument
4160 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline); in radv_pipeline_generate_vgt_gs_mode()
4162 pipeline->shaders[MESA_SHADER_TESS_EVAL] ? in radv_pipeline_generate_vgt_gs_mode()
4163 pipeline->shaders[MESA_SHADER_TESS_EVAL] : in radv_pipeline_generate_vgt_gs_mode()
4164 pipeline->shaders[MESA_SHADER_VERTEX]; in radv_pipeline_generate_vgt_gs_mode()
4168 if (radv_pipeline_has_ngg(pipeline)) in radv_pipeline_generate_vgt_gs_mode()
4171 if (radv_pipeline_has_gs(pipeline)) { in radv_pipeline_generate_vgt_gs_mode()
4173 pipeline->shaders[MESA_SHADER_GEOMETRY]; in radv_pipeline_generate_vgt_gs_mode()
4176 pipeline->device->physical_device->rad_info.chip_class); in radv_pipeline_generate_vgt_gs_mode()
4189 const struct radv_pipeline *pipeline, in radv_pipeline_generate_hw_vs() argument
4200 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline); in radv_pipeline_generate_hw_vs()
4214 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) { in radv_pipeline_generate_hw_vs()
4240 …S_02881C_BYPASS_PRIM_RATE_COMBINER(pipeline->device->physical_device->rad_info.chip_class >= GFX10… in radv_pipeline_generate_hw_vs()
4241 …S_02881C_BYPASS_VTX_RATE_COMBINER(pipeline->device->physical_device->rad_info.chip_class >= GFX10_… in radv_pipeline_generate_hw_vs()
4245 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8) in radv_pipeline_generate_hw_vs()
4252 const struct radv_pipeline *pipeline, in radv_pipeline_generate_hw_es() argument
4266 const struct radv_pipeline *pipeline, in radv_pipeline_generate_hw_ls() argument
4269 unsigned num_lds_blocks = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_lds_blocks; in radv_pipeline_generate_hw_ls()
4278 if (pipeline->device->physical_device->rad_info.chip_class == GFX7 && in radv_pipeline_generate_hw_ls()
4279 pipeline->device->physical_device->rad_info.family != CHIP_HAWAII) in radv_pipeline_generate_hw_ls()
4290 const struct radv_pipeline *pipeline, in radv_pipeline_generate_hw_ngg() argument
4295 radv_pipeline_has_tess(pipeline) ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX; in radv_pipeline_generate_hw_ngg()
4297 …es_type == MESA_SHADER_TESS_EVAL ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[ME… in radv_pipeline_generate_hw_ngg()
4307 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline); in radv_pipeline_generate_hw_ngg()
4323 pipeline->shaders[MESA_SHADER_GEOMETRY]; in radv_pipeline_generate_hw_ngg()
4356 …S_02881C_BYPASS_PRIM_RATE_COMBINER(pipeline->device->physical_device->rad_info.chip_class >= GFX10… in radv_pipeline_generate_hw_ngg()
4357 …S_02881C_BYPASS_VTX_RATE_COMBINER(pipeline->device->physical_device->rad_info.chip_class >= GFX10_… in radv_pipeline_generate_hw_ngg()
4369 struct radv_shader_variant *gs = pipeline->shaders[MESA_SHADER_GEOMETRY]; in radv_pipeline_generate_hw_ngg()
4395 S_028838_INDEX_BUF_EDGE_FLAG_ENA(!radv_pipeline_has_tess(pipeline) && in radv_pipeline_generate_hw_ngg()
4396 !radv_pipeline_has_gs(pipeline)) | in radv_pipeline_generate_hw_ngg()
4398 …S_028838_VERTEX_REUSE_DEPTH(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3 ? 30… in radv_pipeline_generate_hw_ngg()
4409 if (pipeline->device->physical_device->rad_info.chip_class == GFX10 && in radv_pipeline_generate_hw_ngg()
4410 !radv_pipeline_has_tess(pipeline) && in radv_pipeline_generate_hw_ngg()
4424 const struct radv_pipeline *pipeline, in radv_pipeline_generate_hw_hs() argument
4429 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) { in radv_pipeline_generate_hw_hs()
4430 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) { in radv_pipeline_generate_hw_hs()
4455 const struct radv_pipeline *pipeline) in radv_pipeline_generate_vertex_shader() argument
4460 vs = pipeline->shaders[MESA_SHADER_VERTEX]; in radv_pipeline_generate_vertex_shader()
4465 radv_pipeline_generate_hw_ls(cs, pipeline, vs); in radv_pipeline_generate_vertex_shader()
4467 radv_pipeline_generate_hw_es(cs, pipeline, vs); in radv_pipeline_generate_vertex_shader()
4469 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, vs); in radv_pipeline_generate_vertex_shader()
4471 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, vs); in radv_pipeline_generate_vertex_shader()
4477 const struct radv_pipeline *pipeline) in radv_pipeline_generate_tess_shaders() argument
4481 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL]; in radv_pipeline_generate_tess_shaders()
4482 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL]; in radv_pipeline_generate_tess_shaders()
4486 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, tes); in radv_pipeline_generate_tess_shaders()
4488 radv_pipeline_generate_hw_es(cs, pipeline, tes); in radv_pipeline_generate_tess_shaders()
4490 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, tes); in radv_pipeline_generate_tess_shaders()
4493 radv_pipeline_generate_hw_hs(cs, pipeline, tcs); in radv_pipeline_generate_tess_shaders()
4495 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 && in radv_pipeline_generate_tess_shaders()
4496 !radv_pipeline_has_gs(pipeline) && !radv_pipeline_has_ngg(pipeline)) { in radv_pipeline_generate_tess_shaders()
4506 const struct radv_pipeline *pipeline, in radv_pipeline_generate_tess_state() argument
4509 struct radv_shader_variant *tes = radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL); in radv_pipeline_generate_tess_state()
4515 …num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VER… in radv_pipeline_generate_tess_state()
4516 num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches; in radv_pipeline_generate_tess_state()
4522 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) { in radv_pipeline_generate_tess_state()
4573 if (pipeline->device->physical_device->rad_info.has_distributed_tess) { in radv_pipeline_generate_tess_state()
4574 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI || in radv_pipeline_generate_tess_state()
4575 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10) in radv_pipeline_generate_tess_state()
4592 const struct radv_pipeline *pipeline, in radv_pipeline_generate_hw_gs() argument
4636 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) { in radv_pipeline_generate_hw_gs()
4637 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) { in radv_pipeline_generate_hw_gs()
4661 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, pipeline->gs_copy_shader); in radv_pipeline_generate_hw_gs()
4667 const struct radv_pipeline *pipeline) in radv_pipeline_generate_geometry_shader() argument
4671 gs = pipeline->shaders[MESA_SHADER_GEOMETRY]; in radv_pipeline_generate_geometry_shader()
4676 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, gs); in radv_pipeline_generate_geometry_shader()
4678 radv_pipeline_generate_hw_gs(ctx_cs, cs, pipeline, gs); in radv_pipeline_generate_geometry_shader()
4715 const struct radv_pipeline *pipeline) in radv_pipeline_generate_ps_inputs() argument
4717 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT]; in radv_pipeline_generate_ps_inputs()
4718 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline); in radv_pipeline_generate_ps_inputs()
4807 const struct radv_pipeline *pipeline, in radv_compute_db_shader_control() argument
4847 struct radv_pipeline *pipeline) in radv_pipeline_generate_fragment_shader() argument
4851 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]); in radv_pipeline_generate_fragment_shader()
4853 ps = pipeline->shaders[MESA_SHADER_FRAGMENT]; in radv_pipeline_generate_fragment_shader()
4863 radv_compute_db_shader_control(pipeline->device, in radv_pipeline_generate_fragment_shader()
4864 pipeline, ps)); in radv_pipeline_generate_fragment_shader()
4876 radeon_set_context_reg(ctx_cs, R_0286E0_SPI_BARYC_CNTL, pipeline->graphics.spi_baryc_cntl); in radv_pipeline_generate_fragment_shader()
4883 if (pipeline->device->dfsm_allowed) { in radv_pipeline_generate_fragment_shader()
4892 const struct radv_pipeline *pipeline) in radv_pipeline_generate_vgt_vertex_reuse() argument
4894 if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10 || in radv_pipeline_generate_vgt_vertex_reuse()
4895 pipeline->device->physical_device->rad_info.chip_class >= GFX10) in radv_pipeline_generate_vgt_vertex_reuse()
4899 if (radv_pipeline_has_tess(pipeline) && in radv_pipeline_generate_vgt_vertex_reuse()
4900 …radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD)… in radv_pipeline_generate_vgt_vertex_reuse()
4909 const struct radv_pipeline *pipeline) in radv_pipeline_generate_vgt_shader_config() argument
4912 if (radv_pipeline_has_tess(pipeline)) { in radv_pipeline_generate_vgt_shader_config()
4916 if (radv_pipeline_has_gs(pipeline)) in radv_pipeline_generate_vgt_shader_config()
4919 else if (radv_pipeline_has_ngg(pipeline)) in radv_pipeline_generate_vgt_shader_config()
4923 } else if (radv_pipeline_has_gs(pipeline)) { in radv_pipeline_generate_vgt_shader_config()
4926 } else if (radv_pipeline_has_ngg(pipeline)) { in radv_pipeline_generate_vgt_shader_config()
4930 if (radv_pipeline_has_ngg(pipeline)) { in radv_pipeline_generate_vgt_shader_config()
4932 if (pipeline->streamout_shader) in radv_pipeline_generate_vgt_shader_config()
4934 if (radv_pipeline_has_ngg_passthrough(pipeline)) in radv_pipeline_generate_vgt_shader_config()
4936 } else if (radv_pipeline_has_gs(pipeline)) { in radv_pipeline_generate_vgt_shader_config()
4940 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) in radv_pipeline_generate_vgt_shader_config()
4943 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) { in radv_pipeline_generate_vgt_shader_config()
4946 if (radv_pipeline_has_tess(pipeline)) in radv_pipeline_generate_vgt_shader_config()
4947 hs_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.wave_size; in radv_pipeline_generate_vgt_shader_config()
4949 if (pipeline->shaders[MESA_SHADER_GEOMETRY]) { in radv_pipeline_generate_vgt_shader_config()
4950 vs_size = gs_size = pipeline->shaders[MESA_SHADER_GEOMETRY]->info.wave_size; in radv_pipeline_generate_vgt_shader_config()
4951 if (pipeline->gs_copy_shader) in radv_pipeline_generate_vgt_shader_config()
4952 vs_size = pipeline->gs_copy_shader->info.wave_size; in radv_pipeline_generate_vgt_shader_config()
4953 } else if (pipeline->shaders[MESA_SHADER_TESS_EVAL]) in radv_pipeline_generate_vgt_shader_config()
4954 vs_size = pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.wave_size; in radv_pipeline_generate_vgt_shader_config()
4955 else if (pipeline->shaders[MESA_SHADER_VERTEX]) in radv_pipeline_generate_vgt_shader_config()
4956 vs_size = pipeline->shaders[MESA_SHADER_VERTEX]->info.wave_size; in radv_pipeline_generate_vgt_shader_config()
4958 if (radv_pipeline_has_ngg(pipeline)) in radv_pipeline_generate_vgt_shader_config()
5006 struct radv_pipeline *pipeline) in gfx10_pipeline_generate_ge_cntl() argument
5012 if (radv_pipeline_has_tess(pipeline)) { in gfx10_pipeline_generate_ge_cntl()
5013 primgroup_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches; in gfx10_pipeline_generate_ge_cntl()
5014 } else if (radv_pipeline_has_gs(pipeline)) { in gfx10_pipeline_generate_ge_cntl()
5016 &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs_ring_info; in gfx10_pipeline_generate_ge_cntl()
5023 if (radv_pipeline_has_tess(pipeline)) { in gfx10_pipeline_generate_ge_cntl()
5024 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id || in gfx10_pipeline_generate_ge_cntl()
5025 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.uses_prim_id) in gfx10_pipeline_generate_ge_cntl()
5038 const struct radv_pipeline *pipeline, in radv_pipeline_generate_vgt_gs_out() argument
5044 if (radv_pipeline_has_gs(pipeline)) { in radv_pipeline_generate_vgt_gs_out()
5045 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim); in radv_pipeline_generate_vgt_gs_out()
5046 } else if (radv_pipeline_has_tess(pipeline)) { in radv_pipeline_generate_vgt_gs_out()
5047 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.point_mode) { in radv_pipeline_generate_vgt_gs_out()
5050 …gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.primitive_mo… in radv_pipeline_generate_vgt_gs_out()
5058 if (radv_pipeline_has_ngg(pipeline)) in radv_pipeline_generate_vgt_gs_out()
5066 radv_pipeline_generate_pm4(struct radv_pipeline *pipeline, in radv_pipeline_generate_pm4() argument
5071 struct radeon_cmdbuf *ctx_cs = &pipeline->ctx_cs; in radv_pipeline_generate_pm4()
5072 struct radeon_cmdbuf *cs = &pipeline->cs; in radv_pipeline_generate_pm4()
5079 radv_pipeline_generate_depth_stencil_state(ctx_cs, pipeline, pCreateInfo, extra); in radv_pipeline_generate_pm4()
5080 radv_pipeline_generate_blend_state(ctx_cs, pipeline, blend); in radv_pipeline_generate_pm4()
5081 radv_pipeline_generate_raster_state(ctx_cs, pipeline, pCreateInfo); in radv_pipeline_generate_pm4()
5082 radv_pipeline_generate_multisample_state(ctx_cs, pipeline); in radv_pipeline_generate_pm4()
5083 radv_pipeline_generate_vgt_gs_mode(ctx_cs, pipeline); in radv_pipeline_generate_pm4()
5084 radv_pipeline_generate_vertex_shader(ctx_cs, cs, pipeline); in radv_pipeline_generate_pm4()
5086 if (radv_pipeline_has_tess(pipeline)) { in radv_pipeline_generate_pm4()
5087 radv_pipeline_generate_tess_shaders(ctx_cs, cs, pipeline); in radv_pipeline_generate_pm4()
5088 radv_pipeline_generate_tess_state(ctx_cs, pipeline, pCreateInfo); in radv_pipeline_generate_pm4()
5091 radv_pipeline_generate_geometry_shader(ctx_cs, cs, pipeline); in radv_pipeline_generate_pm4()
5092 radv_pipeline_generate_fragment_shader(ctx_cs, cs, pipeline); in radv_pipeline_generate_pm4()
5093 radv_pipeline_generate_ps_inputs(ctx_cs, pipeline); in radv_pipeline_generate_pm4()
5094 radv_pipeline_generate_vgt_vertex_reuse(ctx_cs, pipeline); in radv_pipeline_generate_pm4()
5095 radv_pipeline_generate_vgt_shader_config(ctx_cs, pipeline); in radv_pipeline_generate_pm4()
5097 radv_pipeline_generate_vgt_gs_out(ctx_cs, pipeline, pCreateInfo, extra); in radv_pipeline_generate_pm4()
5099 …if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 && !radv_pipeline_has_ngg(pipe… in radv_pipeline_generate_pm4()
5100 gfx10_pipeline_generate_ge_cntl(ctx_cs, pipeline); in radv_pipeline_generate_pm4()
5102 pipeline->ctx_cs_hash = _mesa_hash_data(ctx_cs->buf, ctx_cs->cdw * 4); in radv_pipeline_generate_pm4()
5109 radv_pipeline_init_vertex_input_state(struct radv_pipeline *pipeline, in radv_pipeline_init_vertex_input_state() argument
5119 pipeline->binding_stride[desc->binding] = desc->stride; in radv_pipeline_init_vertex_input_state()
5120 pipeline->num_vertex_bindings = in radv_pipeline_init_vertex_input_state()
5121 MAX2(pipeline->num_vertex_bindings, desc->binding + 1); in radv_pipeline_init_vertex_input_state()
5126 radv_pipeline_get_streamout_shader(struct radv_pipeline *pipeline) in radv_pipeline_get_streamout_shader() argument
5132 radv_get_shader(pipeline, i); in radv_pipeline_get_streamout_shader()
5142 radv_pipeline_init_shader_stages_state(struct radv_pipeline *pipeline) in radv_pipeline_init_shader_stages_state() argument
5144 struct radv_device *device = pipeline->device; in radv_pipeline_init_shader_stages_state()
5147 pipeline->user_data_0[i] = in radv_pipeline_init_shader_stages_state()
5148 radv_pipeline_stage_to_user_data_0(pipeline, i, in radv_pipeline_init_shader_stages_state()
5151 if (pipeline->shaders[i]) { in radv_pipeline_init_shader_stages_state()
5152 …pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_set… in radv_pipeline_init_shader_stages_state()
5156 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, in radv_pipeline_init_shader_stages_state()
5159 pipeline->graphics.vtx_base_sgpr = pipeline->user_data_0[MESA_SHADER_VERTEX]; in radv_pipeline_init_shader_stages_state()
5160 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4; in radv_pipeline_init_shader_stages_state()
5161 if (radv_get_shader(pipeline, MESA_SHADER_VERTEX)->info.vs.needs_draw_id) in radv_pipeline_init_shader_stages_state()
5162 pipeline->graphics.vtx_emit_num = 3; in radv_pipeline_init_shader_stages_state()
5164 pipeline->graphics.vtx_emit_num = 2; in radv_pipeline_init_shader_stages_state()
5169 radv_pipeline_init(struct radv_pipeline *pipeline, in radv_pipeline_init() argument
5177 pipeline->device = device; in radv_pipeline_init()
5178 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout); in radv_pipeline_init()
5179 assert(pipeline->layout); in radv_pipeline_init()
5181 struct radv_blend_state blend = radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra); in radv_pipeline_init()
5198 struct radv_pipeline_key key = radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, &blend); in radv_pipeline_init()
5200 result = radv_create_shaders(pipeline, device, cache, &key, pStages, in radv_pipeline_init()
5206 pipeline->graphics.spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1); in radv_pipeline_init()
5207 radv_pipeline_init_multisample_state(pipeline, &blend, pCreateInfo); in radv_pipeline_init()
5208 radv_pipeline_init_input_assembly_state(pipeline, pCreateInfo, extra); in radv_pipeline_init()
5209 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo, extra); in radv_pipeline_init()
5210 radv_pipeline_init_raster_state(pipeline, pCreateInfo); in radv_pipeline_init()
5211 radv_pipeline_init_depth_stencil_state(pipeline, pCreateInfo); in radv_pipeline_init()
5228 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT]; in radv_pipeline_init()
5229 if ((pipeline->device->physical_device->rad_info.chip_class <= GFX9 || in radv_pipeline_init()
5251 pipeline->graphics.col_format = blend.spi_shader_col_format; in radv_pipeline_init()
5252 pipeline->graphics.cb_target_mask = blend.cb_target_mask; in radv_pipeline_init()
5254 if (radv_pipeline_has_gs(pipeline) && !radv_pipeline_has_ngg(pipeline)) { in radv_pipeline_init()
5256 pipeline->shaders[MESA_SHADER_GEOMETRY]; in radv_pipeline_init()
5258 radv_pipeline_init_gs_ring_state(pipeline, &gs->info.gs_ring_info); in radv_pipeline_init()
5261 if (radv_pipeline_has_tess(pipeline)) { in radv_pipeline_init()
5262 pipeline->graphics.tess_patch_control_points = in radv_pipeline_init()
5266 radv_pipeline_init_vertex_input_state(pipeline, pCreateInfo); in radv_pipeline_init()
5267 radv_pipeline_init_binning_state(pipeline, pCreateInfo, &blend); in radv_pipeline_init()
5268 radv_pipeline_init_shader_stages_state(pipeline); in radv_pipeline_init()
5269 radv_pipeline_init_scratch(device, pipeline); in radv_pipeline_init()
5272 pipeline->streamout_shader = radv_pipeline_get_streamout_shader(pipeline); in radv_pipeline_init()
5274 radv_pipeline_generate_pm4(pipeline, pCreateInfo, extra, &blend); in radv_pipeline_init()
5290 struct radv_pipeline *pipeline; in radv_graphics_pipeline_create() local
5293 pipeline = vk_zalloc2(&device->vk.alloc, pAllocator, sizeof(*pipeline), 8, in radv_graphics_pipeline_create()
5295 if (pipeline == NULL) in radv_graphics_pipeline_create()
5298 vk_object_base_init(&device->vk, &pipeline->base, in radv_graphics_pipeline_create()
5301 result = radv_pipeline_init(pipeline, device, cache, in radv_graphics_pipeline_create()
5304 radv_pipeline_destroy(device, pipeline, pAllocator); in radv_graphics_pipeline_create()
5308 *pPipeline = radv_pipeline_to_handle(pipeline); in radv_graphics_pipeline_create()
5347 const struct radv_pipeline *pipeline) in radv_pipeline_generate_hw_cs() argument
5349 struct radv_shader_variant *shader = pipeline->shaders[MESA_SHADER_COMPUTE]; in radv_pipeline_generate_hw_cs()
5351 struct radv_device *device = pipeline->device; in radv_pipeline_generate_hw_cs()
5367 const struct radv_pipeline *pipeline) in radv_pipeline_generate_compute_state() argument
5369 struct radv_shader_variant *shader = pipeline->shaders[MESA_SHADER_COMPUTE]; in radv_pipeline_generate_compute_state()
5370 struct radv_device *device = pipeline->device; in radv_pipeline_generate_compute_state()
5400 radv_compute_generate_pm4(struct radv_pipeline *pipeline) in radv_compute_generate_pm4() argument
5402 struct radv_device *device = pipeline->device; in radv_compute_generate_pm4()
5403 struct radeon_cmdbuf *cs = &pipeline->cs; in radv_compute_generate_pm4()
5408 radv_pipeline_generate_hw_cs(cs, pipeline); in radv_compute_generate_pm4()
5409 radv_pipeline_generate_compute_state(cs, pipeline); in radv_compute_generate_pm4()
5411 assert(pipeline->cs.cdw <= pipeline->cs.max_dw); in radv_compute_generate_pm4()
5415 radv_generate_compute_pipeline_key(struct radv_pipeline *pipeline, in radv_generate_compute_pipeline_key() argument
5449 struct radv_pipeline *pipeline; in radv_compute_pipeline_create() local
5452 pipeline = vk_zalloc2(&device->vk.alloc, pAllocator, sizeof(*pipeline), 8, in radv_compute_pipeline_create()
5454 if (pipeline == NULL) in radv_compute_pipeline_create()
5457 vk_object_base_init(&device->vk, &pipeline->base, in radv_compute_pipeline_create()
5460 pipeline->device = device; in radv_compute_pipeline_create()
5461 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout); in radv_compute_pipeline_create()
5462 assert(pipeline->layout); in radv_compute_pipeline_create()
5475 radv_generate_compute_pipeline_key(pipeline, pCreateInfo); in radv_compute_pipeline_create()
5477 result = radv_create_shaders(pipeline, device, cache, &key, pStages, in radv_compute_pipeline_create()
5481 radv_pipeline_destroy(device, pipeline, pAllocator); in radv_compute_pipeline_create()
5485 …pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHA… in radv_compute_pipeline_create()
5486 …pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indir… in radv_compute_pipeline_create()
5487 radv_pipeline_init_scratch(device, pipeline); in radv_compute_pipeline_create()
5489 radv_compute_generate_pm4(pipeline); in radv_compute_pipeline_create()
5491 *pPipeline = radv_pipeline_to_handle(pipeline); in radv_compute_pipeline_create()
5528 static uint32_t radv_get_executable_count(const struct radv_pipeline *pipeline) in radv_get_executable_count() argument
5532 if (!pipeline->shaders[i]) in radv_get_executable_count()
5536 !radv_pipeline_has_ngg(pipeline)) { in radv_get_executable_count()
5547 radv_get_shader_from_executable_index(const struct radv_pipeline *pipeline, int index, gl_shader_st… in radv_get_shader_from_executable_index() argument
5550 if (!pipeline->shaders[i]) in radv_get_shader_from_executable_index()
5554 return pipeline->shaders[i]; in radv_get_shader_from_executable_index()
5560 !radv_pipeline_has_ngg(pipeline)) { in radv_get_shader_from_executable_index()
5563 return pipeline->gs_copy_shader; in radv_get_shader_from_executable_index()
5588 RADV_FROM_HANDLE(radv_pipeline, pipeline, pPipelineInfo->pipeline); in radv_GetPipelineExecutablePropertiesKHR()
5589 const uint32_t total_count = radv_get_executable_count(pipeline); in radv_GetPipelineExecutablePropertiesKHR()
5599 if (!pipeline->shaders[i]) in radv_GetPipelineExecutablePropertiesKHR()
5610 if (!pipeline->shaders[MESA_SHADER_VERTEX]) { in radv_GetPipelineExecutablePropertiesKHR()
5624 if (radv_pipeline_has_tess(pipeline) && !pipeline->shaders[MESA_SHADER_TESS_EVAL]) { in radv_GetPipelineExecutablePropertiesKHR()
5628 } else if (!radv_pipeline_has_tess(pipeline) && !pipeline->shaders[MESA_SHADER_VERTEX]) { in radv_GetPipelineExecutablePropertiesKHR()
5647 pProperties[executable_idx].subgroupSize = pipeline->shaders[i]->info.wave_size; in radv_GetPipelineExecutablePropertiesKHR()
5653 !radv_pipeline_has_ngg(pipeline)) { in radv_GetPipelineExecutablePropertiesKHR()
5654 assert(pipeline->gs_copy_shader); in radv_GetPipelineExecutablePropertiesKHR()
5680 RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline); in radv_GetPipelineExecutableStatisticsKHR()
5682 …struct radv_shader_variant *shader = radv_get_shader_from_executable_index(pipeline, pExecutableIn… in radv_GetPipelineExecutableStatisticsKHR()
5813 RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline); in radv_GetPipelineExecutableInternalRepresentationsKHR()
5815 …struct radv_shader_variant *shader = radv_get_shader_from_executable_index(pipeline, pExecutableIn… in radv_GetPipelineExecutableInternalRepresentationsKHR()
5833 if (radv_use_llvm_for_stage(pipeline->device, stage)) { in radv_GetPipelineExecutableInternalRepresentationsKHR()