Lines Matching refs:a_c
9050 uint16x8_t a_c; variable
9052 a_c = vshrq_n_u16( a, (16 - c));
9053 a_c = _mm_slli_epi16(a_c, (16 - c)); //logical shift provides right "c" bits zeros in a
9054 return _mm_or_si128 (a_c, b_shift); //combine (insert b into a)
9062 uint32x4_t a_c; variable
9064 a_c = vshrq_n_u32( a, (32 - c));
9065 a_c = _mm_slli_epi32(a_c, (32 - c)); //logical shift provides right "c" bits zeros in a
9066 return _mm_or_si128 (a_c, b_shift); //combine (insert b into a)
9074 uint64x2_t a_c; variable
9076 a_c = _mm_srli_epi64(a, (64 - c));
9077 a_c = _mm_slli_epi64(a_c, (64 - c)); //logical shift provides right "c" bits zeros in a
9078 return _mm_or_si128 (a_c, b_shift); //combine (insert b into a)
9170 int16x8_t a_c; variable
9172 a_c = vshlq_n_s16( a, (16 - c));
9173 a_c = _mm_srli_epi16(a_c, (16 - c));
9174 return _mm_or_si128 (b_shift, a_c); //combine (insert b into a)
9183 int32x4_t a_c; variable
9185 a_c = vshlq_n_s32( a, (32 - c));
9186 a_c = _mm_srli_epi32(a_c, (32 - c));
9187 return _mm_or_si128 (b_shift, a_c); //combine (insert b into a)
9196 int64x2_t a_c; variable
9198 a_c = vshlq_n_s64( a, (64 - c));
9199 a_c = _mm_srli_epi64(a_c, (64 - c));
9200 return _mm_or_si128 (b_shift, a_c); //combine (insert b into a)