Lines Matching refs:Src0
541 Operand *Src0 = Instr->getSrc(0); in genTargetHelperCallFor() local
547 Context.insert<InstCast>(CastKind, Src0_32, Src0); in genTargetHelperCallFor()
548 Src0 = Src0_32; in genTargetHelperCallFor()
574 assert(Src0->getType() == IceType_i32); in genTargetHelperCallFor()
575 Call->addArg(Src0); in genTargetHelperCallFor()
602 Operand *Src0 = Instr->getSrc(0); in genTargetHelperCallFor() local
604 const Type SrcTy = Src0->getType(); in genTargetHelperCallFor()
626 Call->addArg(Src0); in genTargetHelperCallFor()
645 Call->addArg(Src0); in genTargetHelperCallFor()
673 Context.insert<InstCast>(InstCast::Zext, Src0AsI32, Src0); in genTargetHelperCallFor()
674 Src0 = Src0AsI32; in genTargetHelperCallFor()
681 Context.insert<InstCast>(InstCast::Zext, Src0AsI32, Src0); in genTargetHelperCallFor()
682 Src0 = Src0AsI32; in genTargetHelperCallFor()
687 Call->addArg(Src0); in genTargetHelperCallFor()
732 Operand *Src0 = IntrinsicCall->getArg(0); in genTargetHelperCallFor() local
734 Ctx->getRuntimeHelperFunc(isInt32Asserting32Or64(Src0->getType()) in genTargetHelperCallFor()
740 Call->addArg(Src0); in genTargetHelperCallFor()
742 if (Src0->getType() == IceType_i64) { in genTargetHelperCallFor()
2358 Variable *Src0 = Func->makeVariable(IceType_i1); in lowerInt1Arithmetic() local
2359 SafeBoolChain Src0Safe = lowerInt1(Src0, Instr->getSrc(0)); in lowerInt1Arithmetic()
2371 Src0 = legalizeToReg(Src0); in lowerInt1Arithmetic()
2379 _and(T, Src0, Src1RF); in lowerInt1Arithmetic()
2382 _orr(T, Src0, Src1RF); in lowerInt1Arithmetic()
2385 _eor(T, Src0, Src1RF); in lowerInt1Arithmetic()
2416 : Src0(NonConstOperand(S0, S1)), Src1(ConstOperand(S0, S1)), in NumericOperandsBase()
2417 Swapped(Src0 == S1 && S0 != S1) { in NumericOperandsBase()
2418 assert(Src0 != nullptr); in NumericOperandsBase()
2420 assert(Src0 != Src1 || S0 == S1); in NumericOperandsBase()
2430 return legalizeToReg(Target, Src0); in src0R()
2434 return legalizeToReg(Target, Swapped ? Src1 : Src0); in unswappedSrc0R()
2442 return legalizeToReg(Target, Swapped ? Src0 : Src1); in unswappedSrc1R()
2448 Operand *const Src0; member in Ice::ARM32::__anon508c538d0b11::NumericOperandsBase
2515 return legalizeToReg(Target, Swapped ? Src0 : Src1); in unswappedSrc1RShAmtImm()
2588 Variable *Dest, Operand *Src0, in lowerInt64Arithmetic() argument
2590 Int32Operands SrcsLo(loOperand(Src0), loOperand(Src1)); in lowerInt64Arithmetic()
2591 Int32Operands SrcsHi(hiOperand(Src0), hiOperand(Src1)); in lowerInt64Arithmetic()
3089 Operand *Src0 = legalizeUndef(Instr->getSrc(0)); in lowerArithmetic() local
3092 lowerInt64Arithmetic(Instr->getOp(), Instr->getDest(), Src0, Src1); in lowerArithmetic()
3130 Variable *Src0R = legalizeToReg(Src0); in lowerArithmetic()
3137 Variable *Src0R = legalizeToReg(Src0); in lowerArithmetic()
3144 Variable *Src0R = legalizeToReg(Src0); in lowerArithmetic()
3151 Variable *Src0R = legalizeToReg(Src0); in lowerArithmetic()
3163 Variable *Src0R = legalizeToReg(Src0); in lowerArithmetic()
3178 Variable *Src0R = legalizeToReg(Src0); in lowerArithmetic()
3192 Variable *Src0R = legalizeToReg(Src0); in lowerArithmetic()
3199 Variable *Src0R = legalizeToReg(Src0); in lowerArithmetic()
3208 Int32Operands Srcs(Src0, Src1); in lowerArithmetic()
3216 Variable *Src0R = legalizeToReg(Src0); in lowerArithmetic()
3302 Variable *Src0R = legalizeToReg(Src0); in lowerArithmetic()
3529 Operand *Src0 = Instr->getSrc(0); in lowerAssign() local
3530 assert(Dest->getType() == Src0->getType()); in lowerAssign()
3532 Src0 = legalizeUndef(Src0); in lowerAssign()
3536 Operand *Src0Lo = legalize(loOperand(Src0), Legal_Reg | Legal_Flex); in lowerAssign()
3542 Operand *Src0Hi = legalize(hiOperand(Src0), Legal_Reg | Legal_Flex); in lowerAssign()
3554 NewSrc = legalize(Src0, Legal_Reg | Legal_Flex, Dest->getRegNum()); in lowerAssign()
3559 NewSrc = legalize(Src0, Legal_Reg); in lowerAssign()
3898 Operand *Src0 = legalizeUndef(Instr->getSrc(0)); in lowerCast() local
3921 auto *Src0R = legalizeToReg(Src0); in lowerCast()
3931 if (Src0->getType() == IceType_i32) { in lowerCast()
3932 Operand *Src0RF = legalize(Src0, Legal_Reg | Legal_Flex); in lowerCast()
3934 } else if (Src0->getType() != IceType_i1) { in lowerCast()
3935 Variable *Src0R = legalizeToReg(Src0); in lowerCast()
3940 lowerInt1ForSelect(T_Lo, Src0, _m1, _0); in lowerCast()
3944 if (Src0->getType() != IceType_i1) { in lowerCast()
3952 } else if (Src0->getType() != IceType_i1) { in lowerCast()
3954 Variable *Src0R = legalizeToReg(Src0); in lowerCast()
3962 lowerInt1ForSelect(T, Src0, _m1, _0); in lowerCast()
3972 auto *Src0R = legalizeToReg(Src0); in lowerCast()
3984 switch (Src0->getType()) { in lowerCast()
3986 assert(Src0->getType() != IceType_i64); in lowerCast()
3987 _uxt(T_Lo, legalizeToReg(Src0)); in lowerCast()
3990 _mov(T_Lo, legalize(Src0, Legal_Reg | Legal_Flex)); in lowerCast()
3993 SafeBoolChain Safe = lowerInt1(T_Lo, Src0); in lowerCast()
4007 } else if (Src0->getType() == IceType_i1) { in lowerCast()
4010 SafeBoolChain Safe = lowerInt1(T, Src0); in lowerCast()
4019 Variable *Src0R = legalizeToReg(Src0); in lowerCast()
4029 auto *Src0R = legalizeToReg(Src0); in lowerCast()
4033 if (Src0->getType() == IceType_i64) in lowerCast()
4034 Src0 = loOperand(Src0); in lowerCast()
4035 Operand *Src0RF = legalize(Src0, Legal_Reg | Legal_Flex); in lowerCast()
4052 assert(Src0->getType() == (IsTrunc ? IceType_f64 : IceType_f32)); in lowerCast()
4053 Variable *Src0R = legalizeToReg(Src0); in lowerCast()
4062 Variable *Src0R = legalizeToReg(Src0); in lowerCast()
4065 assert(typeElementType(Src0->getType()) == IceType_f32); in lowerCast()
4073 const bool Src0IsF32 = isFloat32Asserting32Or64(Src0->getType()); in lowerCast()
4107 Variable *Src0R = legalizeToReg(Src0); in lowerCast()
4115 if (Src0->getType() == IceType_i64) { in lowerCast()
4126 if (Src0->getType() != IceType_i32) { in lowerCast()
4130 Src0R_32, Src0)); in lowerCast()
4131 Src0 = Src0R_32; in lowerCast()
4133 Variable *Src0R = legalizeToReg(Src0); in lowerCast()
4147 Operand *Src0 = Instr->getSrc(0); in lowerCast() local
4148 if (DestTy == Src0->getType()) { in lowerCast()
4149 auto *Assign = InstAssign::create(Func, Dest, Src0); in lowerCast()
4161 assert(Src0->getType() == IceType_v8i1); in lowerCast()
4166 assert(Src0->getType() == IceType_v16i1); in lowerCast()
4172 Variable *Src0R = legalizeToReg(Src0); in lowerCast()
4182 assert(Src0->getType() == IceType_f64); in lowerCast()
4186 Variable *Src0R = legalizeToReg(Src0); in lowerCast()
4198 assert(Src0->getType() == IceType_i64); in lowerCast()
4203 lowerAssign(InstAssign::create(Func, Src64, Src0)); in lowerCast()
4209 assert(Src0->getType() == IceType_i8); in lowerCast()
4214 assert(Src0->getType() == IceType_i16); in lowerCast()
4223 assert(typeWidthInBytes(DestTy) == typeWidthInBytes(Src0->getType())); in lowerCast()
4224 assert(isVectorType(DestTy) == isVectorType(Src0->getType())); in lowerCast()
4226 _mov(T, Src0); in lowerCast()
4240 Variable *Src0 = legalizeToReg(Instr->getSrc(0)); in lowerExtractElement() local
4246 Variable *TSrc0 = makeReg(Src0->getType()); in lowerExtractElement()
4253 _mov(TSrc0, Src0); in lowerExtractElement()
4358 auto *Src0 = legalizeToReg(Instr->getSrc(0)); in lowerFcmp() local
4385 _Vc##CC0_V(&T0, (INV_V) ? Src1 : Src0, (INV_V) ? Src0 : Src1); \ in lowerFcmp()
4386 _Vc##CC1_V(&T1, (INV_V) ? Src0 : Src1, (INV_V) ? Src1 : Src0); \ in lowerFcmp()
4445 TargetARM32::lowerInt64IcmpCond(InstIcmp::ICond Condition, Operand *Src0, in lowerInt64IcmpCond() argument
4449 Int32Operands SrcsLo(loOperand(Src0), loOperand(Src1)); in lowerInt64IcmpCond()
4450 Int32Operands SrcsHi(hiOperand(Src0), hiOperand(Src1)); in lowerInt64IcmpCond()
4517 Src1RFLo = legalizeToReg(loOperand(Src0)); in lowerInt64IcmpCond()
4518 Src1RFHi = legalizeToReg(hiOperand(Src0)); in lowerInt64IcmpCond()
4520 Src0RLo = legalizeToReg(loOperand(Src0)); in lowerInt64IcmpCond()
4521 Src0RHi = legalizeToReg(hiOperand(Src0)); in lowerInt64IcmpCond()
4570 TargetARM32::lowerInt32IcmpCond(InstIcmp::ICond Condition, Operand *Src0, in lowerInt32IcmpCond() argument
4572 Int32Operands Srcs(Src0, Src1); in lowerInt32IcmpCond()
4607 TargetARM32::lowerInt8AndInt16IcmpCond(InstIcmp::ICond Condition, Operand *Src0, in lowerInt8AndInt16IcmpCond() argument
4609 Int32Operands Srcs(Src0, Src1); in lowerInt8AndInt16IcmpCond()
4610 const int32_t ShAmt = 32 - getScalarIntBitWidth(Src0->getType()); in lowerInt8AndInt16IcmpCond()
4616 _lsl(Src0R, legalizeToReg(Src0), ShAmtImm); in lowerInt8AndInt16IcmpCond()
4657 Operand *Src0, in lowerIcmpCond() argument
4659 Src0 = legalizeUndef(Src0); in lowerIcmpCond()
4691 switch (Src0->getType()) { in lowerIcmpCond()
4697 return lowerInt8AndInt16IcmpCond(Condition, Src0, Src1); in lowerIcmpCond()
4699 return lowerInt32IcmpCond(Condition, Src0, Src1); in lowerIcmpCond()
4701 return lowerInt64IcmpCond(Condition, Src0, Src1); in lowerIcmpCond()
4711 auto *Src0 = legalizeToReg(Instr->getSrc(0)); in lowerIcmp() local
4713 const Type SrcTy = Src0->getType(); in lowerIcmp()
4742 _mov(Src0T, Src0); in lowerIcmp()
4744 Src0 = Src0Shl; in lowerIcmp()
4765 _Vc##C_V(T, (INV_V) ? Src1 : Src0, (INV_V) ? Src0 : Src1, is_signed); \ in lowerIcmp()
4801 Variable *Src0 = legalizeToReg(Instr->getSrc(0)); in lowerInsertElement() local
4813 _mov(T, Src0); in lowerInsertElement()
4865 Variable *Src0, Operand *Src1) { in createArithInst() argument
4888 return InstArithmetic::create(Func, Oper, Dest, Src0, Src1); in createArithInst()
5326 Variable *Src0 = legalizeToReg(Instr->getArg(0)); in lowerIntrinsicCall() local
5329 _vqadd(T, Src0, Src1, Unsigned); in lowerIntrinsicCall()
5388 Variable *Src0 = legalizeToReg(Instr->getArg(0)); in lowerIntrinsicCall() local
5391 _vmlap(T, Src0, Src1); in lowerIntrinsicCall()
5398 Variable *Src0 = legalizeToReg(Instr->getArg(0)); in lowerIntrinsicCall() local
5401 _vmulh(T, Src0, Src1, Unsigned); in lowerIntrinsicCall()
5420 Variable *Src0 = legalizeToReg(Instr->getArg(0)); in lowerIntrinsicCall() local
5423 _vqsub(T, Src0, Src1, Unsigned); in lowerIntrinsicCall()
5431 Variable *Src0 = legalizeToReg(Instr->getArg(0)); in lowerIntrinsicCall() local
5434 _vqmovn2(T, Src0, Src1, Unsigned, Saturating); in lowerIntrinsicCall()
5479 Operand *Src0 = formMemoryOperand(Load->getSourceAddress(), Ty); in lowerLoad() local
5484 auto *Assign = InstAssign::create(Func, DestLoad, Src0); in lowerLoad()
5711 Operand *Src0 = ArithInst->getSrc(0); in matchOffsetBase() local
5713 auto *Var0 = llvm::dyn_cast<Variable>(Src0); in matchOffsetBase()
5715 auto *Const0 = llvm::dyn_cast<ConstantInteger32>(Src0); in matchOffsetBase()
5721 assert(llvm::isa<ConstantRelocatable>(Src0)); in matchOffsetBase()
5936 Operand *Src0 = Instr->getRetValue(); in lowerRet() local
5937 Type Ty = Src0->getType(); in lowerRet()
5939 Src0 = legalizeUndef(Src0); in lowerRet()
5940 Variable *R0 = legalizeToReg(loOperand(Src0), RegARM32::Reg_r0); in lowerRet()
5941 Variable *R1 = legalizeToReg(hiOperand(Src0), RegARM32::Reg_r1); in lowerRet()
5945 Variable *S0 = legalizeToReg(Src0, RegARM32::Reg_s0); in lowerRet()
5948 Variable *D0 = legalizeToReg(Src0, RegARM32::Reg_d0); in lowerRet()
5950 } else if (isVectorType(Src0->getType())) { in lowerRet()
5951 Variable *Q0 = legalizeToReg(Src0, RegARM32::Reg_q0); in lowerRet()
5954 Operand *Src0F = legalize(Src0, Legal_Reg | Legal_Flex); in lowerRet()
5978 auto *Src0 = Instr->getSrc(0); in lowerShuffleVector() local
5991 Variable *Src0Var = legalizeToReg(Src0); in lowerShuffleVector()
6005 Variable *Src0R = legalizeToReg(Src0); in lowerShuffleVector()
6012 Variable *Src0R = legalizeToReg(Src0); in lowerShuffleVector()
6020 Variable *Src0R = legalizeToReg(Src0); in lowerShuffleVector()
6033 Variable *Src0R = legalizeToReg(Src0); in lowerShuffleVector()
6041 Variable *Src0R = legalizeToReg(Src0); in lowerShuffleVector()
6056 Variable *Src0R = legalizeToReg(Src0); in lowerShuffleVector()
6063 Variable *Src0R = legalizeToReg(Src0); in lowerShuffleVector()
6071 Variable *Src0R = legalizeToReg(Src0); in lowerShuffleVector()
6079 Variable *Src0R = legalizeToReg(Src0); in lowerShuffleVector()
6086 Variable *Src0R = legalizeToReg(Src0); in lowerShuffleVector()
6106 InstExtractElement::create(Func, ExtElmt, Src0, Index)); in lowerShuffleVector()
6195 Operand *Src0 = Instr->getComparison(); in lowerSwitch() local
6197 if (Src0->getType() == IceType_i64) { in lowerSwitch()
6198 Src0 = legalizeUndef(Src0); in lowerSwitch()
6199 Variable *Src0Lo = legalizeToReg(loOperand(Src0)); in lowerSwitch()
6200 Variable *Src0Hi = legalizeToReg(hiOperand(Src0)); in lowerSwitch()
6214 Variable *Src0Var = legalizeToReg(Src0); in lowerSwitch()
6218 const size_t ShiftAmt = 32 - getScalarIntBitWidth(Src0->getType()); in lowerSwitch()