Lines Matching refs:Src0
817 Operand *&Src0, Operand *&Src1) {
818 if (Src0 == LoadDest && Src1 != LoadDest) {
819 Src0 = LoadSrc;
822 if (Src0 != LoadDest && Src1 == LoadDest) {
868 Operand *Src0 = Arith->getSrc(0);
870 if (canFoldLoadIntoBinaryInst(LoadSrc, LoadDest, Src0, Src1)) {
872 Arith->getDest(), Src0, Src1);
875 Operand *Src0 = Icmp->getSrc(0);
877 if (canFoldLoadIntoBinaryInst(LoadSrc, LoadDest, Src0, Src1)) {
879 Icmp->getDest(), Src0, Src1);
882 Operand *Src0 = Fcmp->getSrc(0);
884 if (canFoldLoadIntoBinaryInst(LoadSrc, LoadDest, Src0, Src1)) {
886 Fcmp->getDest(), Src0, Src1);
889 Operand *Src0 = Select->getTrueOperand();
891 if (canFoldLoadIntoBinaryInst(LoadSrc, LoadDest, Src0, Src1)) {
893 Select->getCondition(), Src0, Src1);
897 auto *Src0 = llvm::dyn_cast<Variable>(Cast->getSrc(0));
898 if (Src0 == LoadDest) {
1668 bool TargetX86Base<TraitsType>::optimizeScalarMul(Variable *Dest, Operand *Src0,
1677 _mov(T, Src0);
1688 _mov(T, Src0);
1735 if (typeWidthInBytes(Src0->getType()) < typeWidthInBytes(T->getType())) {
1736 Operand *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
1739 _mov(T, Src0);
1984 Operand *Src0 = legalize(Instr->getSrc(0));
1988 if (!llvm::isa<Variable>(Src0) && llvm::isa<Variable>(Src1)) {
1989 std::swap(Src0, Src1);
1992 if (llvm::isa<Constant>(Src0) && !llvm::isa<Constant>(Src1)) {
1993 std::swap(Src0, Src1);
1998 if (!Instr->isLastUse(Src0) && Instr->isLastUse(Src1)) {
1999 std::swap(Src0, Src1);
2025 Operand *Src0Lo = loOperand(Src0);
2026 Operand *Src0Hi = hiOperand(Src0);
2138 _movp(T, Src0);
2144 _movp(T, Src0);
2150 _movp(T, Src0);
2156 _movp(T, Src0);
2162 _movp(T, Src0);
2172 _movp(T, Src0);
2173 _pmull(T, Src0 == Src1 ? T : Src1);
2205 _movp(T1, Src0);
2206 _pshufd(T2, Src0, Mask1030);
2222 _movp(T, Src0);
2229 _movp(T, Src0);
2236 _movp(T, Src0);
2248 _movp(T, Src0);
2254 _movp(T, Src0);
2260 _movp(T, Src0);
2261 _mulps(T, Src0 == Src1 ? T : Src1);
2266 _movp(T, Src0);
2290 auto *Var = legalizeToReg(Src0);
2297 _mov(T, Src0);
2302 _mov(T, Src0);
2307 _mov(T, Src0);
2312 _mov(T, Src0);
2317 _mov(T, Src0);
2323 if (optimizeScalarMul(Dest, Src0, C->getValue()))
2329 _mov(T, Src0, Traits::RegisterSet::Reg_al);
2331 _imul(T, Src0 == Src1 ? T : Src1);
2335 _imul_imm(T, Src0, ImmConst);
2338 _mov(T, Src0);
2339 _imul(T, Src0 == Src1 ? T : Src1);
2344 _mov(T, Src0);
2352 _mov(T, Src0);
2360 _mov(T, Src0);
2394 _mov(T, Src0, Eax);
2419 _mov(T, Src0);
2427 _add(T, Src0);
2441 _mov(T, Src0, Traits::getRaxOrDie());
2445 _mov(T, Src0, Traits::RegisterSet::Reg_eax);
2449 _mov(T, Src0, Traits::RegisterSet::Reg_ax);
2453 _mov(T, Src0, Traits::RegisterSet::Reg_al);
2487 _mov(T, Src0, Eax);
2526 _mov(T, Src0);
2531 _add(T, Src0);
2533 _sub(T, Src0);
2564 _mov(T, Src0, Eax);
2579 _mov(T, Src0);
2584 _mov(T, Src0);
2589 _mov(T, Src0);
2590 _mulss(T, Src0 == Src1 ? T : Src1);
2594 _mov(T, Src0);
2645 Operand *Src0 = legalize(Cond, Legal_Reg | Legal_Mem);
2647 _cmp(Src0, Zero);
3024 Operand *Src0 = legalizeUndef(Instr->getSrc(0));
3025 if (!Traits::Is64Bit && Src0->getType() == IceType_i64)
3026 Src0 = loOperand(Src0);
3027 Operand *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
3033 Operand *Src0 = legalizeUndef(Instr->getSrc(0));
3034 if (!Traits::Is64Bit && Src0->getType() == IceType_i64)
3035 Src0 = loOperand(Src0);
3036 Operand *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
3148 Operand *Src0 = Instr->getSrc(0);
3149 if (isVectorType(Src0->getType())) {
3151 } else if (Src0->getType() == IceType_i64 ||
3152 (!Traits::Is64Bit && Src0->getType() == IceType_i32)) {
3155 Operand *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
3177 Operand *Src0 = Instr->getSrc(0);
3178 if (DestTy == Src0->getType()) {
3179 auto *Assign = InstAssign::create(Func, Dest, Src0);
3194 Variable *Src0R = legalizeToReg(Src0);
3200 assert(Src0->getType() == IceType_f64);
3202 Variable *Src0R = legalizeToReg(Src0);
3207 Operand *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
3241 assert(Src0->getType() == IceType_i64);
3243 Operand *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
3248 Src0 = legalize(Src0);
3249 if (llvm::isa<X86OperandMem>(Src0)) {
3251 _movq(T, Src0);
3271 _mov(T_Lo, loOperand(Src0));
3277 _mov(T_Hi, hiOperand(Src0));
3292 if (Src0->getType() == IceType_i32) {
3298 Operand *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
3303 _movp(Dest, legalizeToReg(Src0));
3408 Operand *Src0 = Fcmp->getSrc(0);
3442 std::swap(Src0, Src1);
3446 Src0 = legalize(Src0);
3449 _mov(T, Src0);
3513 Operand *Src0 = Fcmp->getSrc(0);
3524 std::swap(Src0, Src1);
3534 Operand *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
3586 Operand *Src0 = legalize(Icmp->getSrc(0));
3597 if (!Traits::Is64Bit && Src0->getType() == IceType_i64) {
3615 Operand *Src0RM = legalizeSrc0ForCmp(Src0, Src1);
3623 Operand *Src0 = legalize(Icmp->getSrc(0));
3630 Type Ty = Src0->getType();
3650 lowerCast(InstCast::create(Func, InstCast::Sext, NewSrc0, Src0));
3652 Src0 = NewSrc0;
3659 Operand *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
3743 Operand *Src0 = legalize(Icmp->getSrc(0));
3766 Src0LoRM = legalize(loOperand(Src0), Legal_Reg | Legal_Mem);
3771 Src0HiRM = legalize(hiOperand(Src0), Legal_Reg | Legal_Mem);
3780 Src0LoRM = legalize(loOperand(Src0), Legal_Reg | Legal_Mem);
3781 Src0HiRM = legalize(hiOperand(Src0), Legal_Reg | Legal_Mem);
3940 Operand *Src0 = legalize(Arith->getSrc(0));
3948 _mov(T, Src0);
3958 _mov(T, Src0);
4534 Operand *Src0 = Instr->getArg(0);
4537 auto *T = makeReg(Src0->getType());
4538 auto *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
4546 Operand *Src0 = Instr->getArg(0);
4549 auto *T = makeReg(Src0->getType());
4550 auto *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
4573 Operand *Src0 = Instr->getArg(0);
4577 auto *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
4585 Operand *Src0 = Instr->getArg(0);
4589 auto *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
4597 Operand *Src0 = Instr->getArg(0);
4601 auto *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
4609 Operand *Src0 = Instr->getArg(0);
4613 auto *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
4621 Operand *Src0 = Instr->getArg(0);
4625 auto *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
4633 Operand *Src0 = Instr->getArg(0);
4637 auto *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
4645 Operand *Src0 = Instr->getArg(0);
4649 auto *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
5697 Operand *Src0 = ArithInst->getSrc(0);
5699 auto *Var0 = llvm::dyn_cast<Variable>(Src0);
5701 auto *Const0 = llvm::dyn_cast<ConstantInteger32>(Src0);
5703 auto *Reloc0 = llvm::dyn_cast<ConstantRelocatable>(Src0);
6052 Operand *Src0 = formMemoryOperand(Load->getSourceAddress(), Ty);
6053 doMockBoundsCheck(Src0);
6054 auto *Assign = InstAssign::create(Func, DestLoad, Src0);
6180 Operand *Src0, SizeT Index0, SizeT Index1, Operand *Src1, SizeT Index2,
6187 const Type SrcTy = Src0->getType();
6190 auto *Src0R = legalizeToReg(Src0);
6201 Operand *Src0, SizeT Index0, Operand *Src1, SizeT Index1) {
6202 return lowerShuffleVector_TwoFromSameSrc(Src0, Index0, IGNORE_INDEX, Src1,
6260 Variable *Dest, Operand *Src0, Operand *Src1, int8_t Idx0, int8_t Idx1,
6287 auto *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
6322 auto *Src0 = Instr->getSrc(0);
6339 auto *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
6349 auto *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
6360 auto *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
6370 auto *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
6400 lowerShuffleVector_UsingPshufb(Dest, Src0, Src1, Index0, Index1, Index2,
6414 auto *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
6423 auto *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
6433 auto *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
6442 auto *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
6466 Dest, Src0, Src1, TO_BYTE_INDEX(Index0), TO_BYTE_INDEX(Index0) + 1,
6491 T = lowerShuffleVector_AllFromSameSrc(Src0, Index0, Index1, Index2,
6496 auto *Unified = lowerShuffleVector_UnifyFromDifferentSrcs(Src0, Index2,
6498 T = lowerShuffleVector_TwoFromSameSrc(Src0, Index0, Index1, Unified,
6504 Src0, Index3);
6505 T = lowerShuffleVector_TwoFromSameSrc(Src0, Index0, Index1, Unified,
6510 T = lowerShuffleVector_TwoFromSameSrc(Src0, Index0, Index1, Src1,
6515 auto *Unified = lowerShuffleVector_UnifyFromDifferentSrcs(Src0, Index0,
6518 Unified, UNIFIED_INDEX_0, UNIFIED_INDEX_1, Src0, Index2, Index3);
6525 auto *Src0R = legalizeToReg(Src0);
6531 Src0, Index0, Src1, Index1);
6537 Src0, Index0, Src1, Index1);
6539 Src0, Index2, Src1, Index3);
6549 Src0, Index0, Src1, Index1);
6555 Src0, Index0, Src1, Index1);
6557 Src1, Index2, Src0, Index3);
6565 auto *Unified = lowerShuffleVector_UnifyFromDifferentSrcs(Src0, Index0,
6573 Src0, Index1);
6575 Unified, UNIFIED_INDEX_0, UNIFIED_INDEX_1, Src0, Index2, Index3);
6581 Src1, Index0, Src0, Index1);
6587 Src1, Index0, Src0, Index1);
6589 Src0, Index2, Src1, Index3);
6599 auto *Src1RM = legalize(Src0, Legal_Reg | Legal_Mem);
6606 Src1, Index0, Src0, Index1);
6612 Src1, Index0, Src0, Index1);
6614 Src1, Index2, Src0, Index3);
6623 Src0, Index1);
6629 T = lowerShuffleVector_TwoFromSameSrc(Src1, Index0, Index1, Src0,
6634 auto *Unified = lowerShuffleVector_UnifyFromDifferentSrcs(Src0, Index2,
6642 Src0, Index3);
6671 InstExtractElement::create(Func, ExtElmt, Src0, Index));
7114 Operand *Src0 = Instr->getComparison();
7119 if (!Traits::Is64Bit && Src0->getType() == IceType_i64) {
7120 Src0 = legalize(Src0); // get Base/Index into physical registers
7121 Operand *Src0Lo = loOperand(Src0);
7122 Operand *Src0Hi = hiOperand(Src0);
7153 Src0 = Src0Lo;
7163 lowerCaseCluster(CaseClusters.front(), Src0, DoneCmp, DefaultTarget);
7168 Variable *Comparison = legalizeToReg(Src0);
7436 Operand *Src0 = Arith->getSrc(0);
7443 scalarizeArithmetic(Arith->getOp(), Dest, Src0, Src1);
7458 scalarizeArithmetic(Arith->getOp(), Dest, Src0, Src1);
7482 Operand *Src0 = Cast->getSrc(0);
7483 const Type SrcType = Src0->getType();
7554 if (DestTy == Src0->getType())
7560 assert(Src0->getType() == IceType_v8i1);
7565 assert(Src0->getType() == IceType_v16i1);
7570 assert(Src0->getType() == IceType_i8);
7574 Context.insert<InstCast>(InstCast::Zext, Src0AsI32, Src0);
7575 Src0 = Src0AsI32;
7578 assert(Src0->getType() == IceType_i16);
7582 Context.insert<InstCast>(InstCast::Zext, Src0AsI32, Src0);
7583 Src0 = Src0AsI32;
7590 Call->addArg(Src0);
8124 Operand *TargetX86Base<TraitsType>::legalizeSrc0ForCmp(Operand *Src0,
8133 return legalize(Src0, IsSrc1ImmOrReg ? (Legal_Reg | Legal_Mem) : Legal_Reg);