Lines Matching refs:x0
67 adr x0, _start /* x0 <- Runtime value of _start */
69 sub x9, x0, x1 /* x9 <- Run-vs-link offset */
73 ldp x0, x1, [x2], #16 /* (x0, x1) <- (Link location, fixup) */
78 add x0, x0, x9
80 str x4, [x0]
95 adr x0, vectors
105 3: set_vbar vbar_el3, x0
106 mrs x0, scr_el3
107 orr x0, x0, #0xf /* SCR_EL3.NS|IRQ|FIQ|EA */
108 msr scr_el3, x0
111 ldr x0, =COUNTER_FREQUENCY
112 msr cntfrq_el0, x0 /* Initialize CNTFRQ */
115 2: set_vbar vbar_el2, x0
116 mov x0, #0x33ff
117 msr cptr_el2, x0 /* Enable FP/SIMD */
119 1: set_vbar vbar_el1, x0
120 mov x0, #3 << 20
121 msr cpacr_el1, x0 /* Enable FP/SIMD */
132 mrs x0, S3_1_c15_c2_1 /* cpuectlr_el1 */
133 orr x0, x0, #0x40
134 msr S3_1_c15_c2_1, x0
152 branch_if_master x0, x1, master_cpu
156 branch_if_master x0, x1, master_cpu
164 ldr x0, [x1]
165 cbz x0, slave_cpu
166 br x0 /* branch to the given address */
175 mrs x0, sctlr_el3
178 mrs x0, sctlr_el2
181 mrs x0, sctlr_el1
185 and x0, x0, x1
189 msr sctlr_el3, x0
192 msr sctlr_el2, x0
195 msr sctlr_el1, x0
212 branch_if_a53_core x0, apply_a53_core_errata
215 branch_if_a57_core x0, apply_a57_core_errata
223 mrs x0, midr_el1
224 tst x0, #(0xf << 20)
227 mrs x0, midr_el1
228 and x0, x0, #0xf
229 cmp x0, #3
232 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
234 orr x0, x0, #1 << 44
235 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
242 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
244 orr x0, x0, #1 << 49
246 orr x0, x0, #3 << 25
248 orr x0, x0, #3 << 27
249 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
253 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
255 orr x0, x0, #1 << 59
256 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
260 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
264 orr x0, x0, #1 << 38
265 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
269 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
274 orr x0, x0, #1 << 4
275 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
279 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
281 and x0, x0, #0xE
282 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
293 branch_if_slave x0, 1f
294 ldr x0, =GICD_BASE
298 ldr x0, =GICR_BASE
301 ldr x0, =GICD_BASE
308 branch_if_master x0, x1, 2f
317 ldr x0, =GICC_BASE
348 ldr x0, =GICD_BASE
359 adr x0, vectors
361 3: msr vbar_el3, x0
363 2: msr vbar_el2, x0
365 1: msr vbar_el1, x0