Lines Matching refs:cru
6 #include <dt-bindings/clock/px30-cru.h>
46 clocks = <&cru ARMCLK>;
58 clocks = <&cru ARMCLK>;
70 clocks = <&cru ARMCLK>;
82 clocks = <&cru ARMCLK>;
209 clocks = <&cru HCLK_HOST>,
210 <&cru HCLK_OTG>,
211 <&cru SCLK_OTG_ADP>;
216 clocks = <&cru HCLK_SDMMC>,
217 <&cru SCLK_SDMMC>;
222 clocks = <&cru ACLK_GMAC>,
223 <&cru PCLK_GMAC>,
224 <&cru SCLK_MAC_REF>,
225 <&cru SCLK_GMAC_RX_TX>;
230 clocks = <&cru HCLK_NANDC>,
231 <&cru HCLK_EMMC>,
232 <&cru HCLK_SDIO>,
233 <&cru HCLK_SFC>,
234 <&cru SCLK_EMMC>,
235 <&cru SCLK_NANDC>,
236 <&cru SCLK_SDIO>,
237 <&cru SCLK_SFC>;
243 clocks = <&cru ACLK_VPU>,
244 <&cru HCLK_VPU>,
245 <&cru SCLK_CORE_VPU>;
250 clocks = <&cru ACLK_RGA>,
251 <&cru ACLK_VOPB>,
252 <&cru ACLK_VOPL>,
253 <&cru DCLK_VOPB>,
254 <&cru DCLK_VOPL>,
255 <&cru HCLK_RGA>,
256 <&cru HCLK_VOPB>,
257 <&cru HCLK_VOPL>,
258 <&cru PCLK_MIPI_DSI>,
259 <&cru SCLK_RGA_CORE>,
260 <&cru SCLK_VOPB_PWM>;
266 clocks = <&cru ACLK_CIF>,
267 <&cru ACLK_ISP>,
268 <&cru HCLK_CIF>,
269 <&cru HCLK_ISP>,
270 <&cru SCLK_ISP>;
277 clocks = <&cru SCLK_GPU>;
324 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>;
339 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>;
379 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
394 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
409 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
424 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
439 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
453 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
466 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
479 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
492 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
506 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
521 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
535 clocks = <&cru PCLK_WDT_NS>;
543 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
554 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
565 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
576 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
587 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
598 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
609 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
620 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
632 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
647 clocks = <&cru ACLK_DMAC>;
658 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
660 resets = <&cru SRST_SARADC_P>;
668 clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>,
669 <&cru PCLK_OTP_PHY>;
671 resets = <&cru SRST_OTP_PHY>;
689 cru: clock-controller@ff2b0000 { label
690 compatible = "rockchip,px30-cru";
712 clocks = <&pmucru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>;
715 resets = <&cru SRST_MIPIDSIPHY_P>;
727 clocks = <&cru HCLK_OTG>;
742 clocks = <&cru HCLK_HOST>;
752 clocks = <&cru HCLK_HOST>;
763 clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>,
764 <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_MAC_REF>,
765 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
766 <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RMII>;
776 resets = <&cru SRST_GMAC_A>;
785 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
786 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
800 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
801 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
815 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
816 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
830 clocks = <&cru PCLK_MIPI_DSI>, <&dsi_dphy>;
832 resets = <&cru SRST_MIPIDSI_HOST_P>;
868 clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>,
869 <&cru HCLK_VOPB>;
871 resets = <&cru SRST_VOPB_A>, <&cru SRST_VOPB_H>, <&cru SRST_VOPB>;
894 clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>;
905 clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>,
906 <&cru HCLK_VOPL>;
908 resets = <&cru SRST_VOPL_A>, <&cru SRST_VOPL_H>, <&cru SRST_VOPL>;
931 clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>;
1062 clocks = <&cru PCLK_GPIO1>;
1074 clocks = <&cru PCLK_GPIO2>;
1086 clocks = <&cru PCLK_GPIO3>;