40 		writel(0x04008050, &mmdc0->mdscr);  in precharge_all()
41 		wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0);  in precharge_all()
45 		writel(0x04008058, &mmdc0->mdscr);  in precharge_all()
46 		wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0);  in precharge_all()
156 	writel(0x00808231, &mmdc0->mdscr);  in mmdc_do_write_level_calibration()
211 	writel((ddr_mr1 << 16) + 0x8031, &mmdc0->mdscr);  in mmdc_do_write_level_calibration()
243 	writel(0, &mmdc0->mdscr);  in mmdc_do_write_level_calibration()
299 		writel(0x00008020, &mmdc0->mdscr);  in mmdc_do_dqs_calibration()
301 		writel(0x00008028, &mmdc0->mdscr);  in mmdc_do_dqs_calibration()
304 	wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0);  in mmdc_do_dqs_calibration()
549 	writel(0x0, &mmdc0->mdscr);	/* CS0 */  in mmdc_do_dqs_calibration()
552 	wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 0, 100, 0);  in mmdc_do_dqs_calibration()
1137 	mmdc0->mdscr = (u32)(1 << 15); /* config request */  in mx6_lpddr2_cfg()
1181 		mmdc0->mdscr = MR(63, 0, 3, cs);  in mx6_lpddr2_cfg()
1186 		mmdc0->mdscr = MR(val, 0, 3, cs);  in mx6_lpddr2_cfg()
1189 		mmdc0->mdscr = MR(val, 0, 3, cs);  in mx6_lpddr2_cfg()
1192 		mmdc0->mdscr = MR(val, 0, 3, cs);  in mx6_lpddr2_cfg()
1195 		mmdc0->mdscr = MR(val, 0, 3, cs);  in mx6_lpddr2_cfg()
1215 	mmdc0->mdscr = 0x00000000;  in mx6_lpddr2_cfg()
1429 	mmdc0->mdscr = (u32)(1 << 15); /* config request */  in mx6_ddr3_cfg()
1478 		mmdc0->mdscr = MR(val, 2, 3, cs);  in mx6_ddr3_cfg()
1481 		mmdc0->mdscr = MR(0, 3, 3, cs);  in mx6_ddr3_cfg()
1486 		mmdc0->mdscr = MR(val, 1, 3, cs);  in mx6_ddr3_cfg()
1493 		mmdc0->mdscr = MR(val, 0, 3, cs);  in mx6_ddr3_cfg()
1496 		mmdc0->mdscr = MR(val, 0, 4, cs);  in mx6_ddr3_cfg()
1520 	mmdc0->mdscr = 0x00000000;  in mx6_ddr3_cfg()