Lines Matching refs:freq
345 unsigned long freq = 0; in ks_clk_get_rate() local
349 freq = pll_freq_get(CORE_PLL); in ks_clk_get_rate()
352 freq = pll_freq_get(PASS_PLL); in ks_clk_get_rate()
356 freq = pll_freq_get(TETRIS_PLL); in ks_clk_get_rate()
359 freq = pll_freq_get(DDR3A_PLL); in ks_clk_get_rate()
363 freq = pll_freq_get(DDR3B_PLL); in ks_clk_get_rate()
367 freq = pll_freq_get(UART_PLL); in ks_clk_get_rate()
371 freq = pll_freq_get(CORE_PLL) / pll0div_read(1); in ks_clk_get_rate()
377 freq = pll_freq_get(CORE_PLL) / pll0div_read(3); in ks_clk_get_rate()
380 freq = pll_freq_get(CORE_PLL) / pll0div_read(4); in ks_clk_get_rate()
383 freq = ks_clk_get_rate(sys_clk0_clk) / 2; in ks_clk_get_rate()
386 freq = ks_clk_get_rate(sys_clk0_clk) / 3; in ks_clk_get_rate()
389 freq = ks_clk_get_rate(sys_clk0_clk) / 4; in ks_clk_get_rate()
392 freq = ks_clk_get_rate(sys_clk0_clk) / 6; in ks_clk_get_rate()
395 freq = ks_clk_get_rate(sys_clk0_clk) / 8; in ks_clk_get_rate()
398 freq = ks_clk_get_rate(sys_clk0_clk) / 12; in ks_clk_get_rate()
401 freq = ks_clk_get_rate(sys_clk0_clk) / 24; in ks_clk_get_rate()
404 freq = ks_clk_get_rate(sys_clk1_clk) / 3; in ks_clk_get_rate()
407 freq = ks_clk_get_rate(sys_clk1_clk) / 4; in ks_clk_get_rate()
410 freq = ks_clk_get_rate(sys_clk1_clk) / 6; in ks_clk_get_rate()
413 freq = ks_clk_get_rate(sys_clk1_clk) / 12; in ks_clk_get_rate()
419 return freq; in ks_clk_get_rate()