39 	void __iomem *ddr_regs;  in ar934x_ddr_init()  local
44 	ddr_regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,  in ar934x_ddr_init()
66 			writel(0xe59, ddr_regs + AR934X_DDR_REG_DDR2_CONFIG);  in ar934x_ddr_init()
69 			writel(0x10, ddr_regs + AR71XX_DDR_REG_CONTROL);  in ar934x_ddr_init()
72 			writel(0x20, ddr_regs + AR71XX_DDR_REG_CONTROL);  in ar934x_ddr_init()
75 			writel(ctl, ddr_regs + AR934X_DDR_REG_CTL_CONF);  in ar934x_ddr_init()
82 		writel(0x13b, ddr_regs + AR934X_DDR_REG_CTL_CONF);  in ar934x_ddr_init()
86 		writel(0x13b, ddr_regs + 0x118);  in ar934x_ddr_init()
92 	writel(memcfg->config1, ddr_regs + AR71XX_DDR_REG_CONFIG);  in ar934x_ddr_init()
95 	writel(memcfg->config2, ddr_regs + AR71XX_DDR_REG_CONFIG2);  in ar934x_ddr_init()
98 	writel(0x8, ddr_regs + AR71XX_DDR_REG_CONTROL);  in ar934x_ddr_init()
101 	writel(memcfg->mode | 0x100, ddr_regs + AR71XX_DDR_REG_MODE);  in ar934x_ddr_init()
104 	writel(0x1, ddr_regs + AR71XX_DDR_REG_CONTROL);  in ar934x_ddr_init()
108 		writel(memcfg->mode | 0x100, ddr_regs + AR71XX_DDR_REG_EMR);  in ar934x_ddr_init()
111 		writel(0x2, ddr_regs + AR71XX_DDR_REG_CONTROL);  in ar934x_ddr_init()
116 		writel(0x402, ddr_regs + AR71XX_DDR_REG_EMR);  in ar934x_ddr_init()
120 	writel(0x2, ddr_regs + AR71XX_DDR_REG_CONTROL);  in ar934x_ddr_init()
123 	writel(0x8, ddr_regs + AR71XX_DDR_REG_CONTROL);  in ar934x_ddr_init()
126 	writel(memcfg->mode, ddr_regs + AR71XX_DDR_REG_MODE);  in ar934x_ddr_init()
129 	writel(0x1, ddr_regs + AR71XX_DDR_REG_CONTROL);  in ar934x_ddr_init()
132 	writel(0x412c /* FIXME */, ddr_regs + AR71XX_DDR_REG_REFRESH);  in ar934x_ddr_init()
135 	writel(memcfg->tap, ddr_regs + AR71XX_DDR_REG_TAP_CTRL0);  in ar934x_ddr_init()
136 	writel(memcfg->tap, ddr_regs + AR71XX_DDR_REG_TAP_CTRL1);  in ar934x_ddr_init()
141 			       ddr_regs + AR934X_DDR_REG_TAP_CTRL2);  in ar934x_ddr_init()
143 			       ddr_regs + AR934X_DDR_REG_TAP_CTRL3);  in ar934x_ddr_init()
147 	writel(cycle, ddr_regs + AR71XX_DDR_REG_RD_CYCLE);  in ar934x_ddr_init()
150 	writel(0x74444444, ddr_regs + AR934X_DDR_REG_BURST);  in ar934x_ddr_init()
153 	writel(0x222, ddr_regs + AR934X_DDR_REG_BURST2);  in ar934x_ddr_init()
156 	writel(0xfffff, ddr_regs + AR934X_DDR_REG_TIMEOUT_MAX);  in ar934x_ddr_init()