190 	void __iomem *ddr_regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,  in qca956x_ddr_init()  local
205 	writel(0x10, ddr_regs + AR71XX_DDR_REG_CONTROL);  in qca956x_ddr_init()
208 	writel(0x20, ddr_regs + AR71XX_DDR_REG_CONTROL);  in qca956x_ddr_init()
211 	writel(ctl_config, ddr_regs + QCA956X_DDR_REG_CTL_CONF);  in qca956x_ddr_init()
214 	writel(cycle_val, ddr_regs + AR71XX_DDR_REG_RD_CYCLE);  in qca956x_ddr_init()
217 	writel(0x74444444, ddr_regs + QCA956X_DDR_REG_BURST);  in qca956x_ddr_init()
220 	writel(0x44444444, ddr_regs + QCA956X_DDR_REG_BURST2);  in qca956x_ddr_init()
223 	writel(DDR_FSM_WAIT_CTRL_VAL, ddr_regs + QCA956X_DDR_REG_FSM_WAIT_CTRL);  in qca956x_ddr_init()
226 	writel(0xfffff, ddr_regs + QCA956X_DDR_REG_TIMEOUT_MAX);  in qca956x_ddr_init()
229 	writel(ddr_config, ddr_regs + AR71XX_DDR_REG_CONFIG);  in qca956x_ddr_init()
232 	writel(ddr_config2, ddr_regs + AR71XX_DDR_REG_CONFIG2);  in qca956x_ddr_init()
235 	writel(ddr_config3, ddr_regs + QCA956X_DDR_REG_DDR3_CONFIG);  in qca956x_ddr_init()
238 	writel(CFG_DDR2_EN_TWL_VAL, ddr_regs + QCA956X_DDR_REG_DDR2_CONFIG);  in qca956x_ddr_init()
241 	writel(ddr_config2 | 0x80, ddr_regs + AR71XX_DDR_REG_CONFIG2);	/* CKE Enable */  in qca956x_ddr_init()
244 	writel(0x8, ddr_regs + AR71XX_DDR_REG_CONTROL);	/* Precharge */  in qca956x_ddr_init()
247 	writel(0, ddr_regs + QCA956X_DDR_REG_DDR2_EMR2);  in qca956x_ddr_init()
248 	writel(0x10, ddr_regs + AR71XX_DDR_REG_CONTROL);	/* EMR2 */  in qca956x_ddr_init()
251 	writel(0, ddr_regs + QCA956X_DDR_REG_DDR2_EMR3);  in qca956x_ddr_init()
252 	writel(0x20, ddr_regs + AR71XX_DDR_REG_CONTROL);	/* EMR3 */  in qca956x_ddr_init()
256 	writel(CFG_DDR2_EXT_MODE_VAL2, ddr_regs + AR71XX_DDR_REG_EMR);  in qca956x_ddr_init()
259 	writel(0x2, ddr_regs + AR71XX_DDR_REG_CONTROL); /* EMR write */  in qca956x_ddr_init()
262 	writel(mod_val_init, ddr_regs + AR71XX_DDR_REG_MODE);  in qca956x_ddr_init()
265 	writel(0x1, ddr_regs + AR71XX_DDR_REG_CONTROL);	/* MR Write */  in qca956x_ddr_init()
268 	writel(0x8, ddr_regs + AR71XX_DDR_REG_CONTROL);	/* Precharge */  in qca956x_ddr_init()
271 	writel(0x4, ddr_regs + AR71XX_DDR_REG_CONTROL);	/* Auto Refresh */  in qca956x_ddr_init()
274 	writel(0x4, ddr_regs + AR71XX_DDR_REG_CONTROL);	/* Auto Refresh */  in qca956x_ddr_init()
278 	writel(mod_val, ddr_regs + AR71XX_DDR_REG_MODE);  in qca956x_ddr_init()
281 	writel(0x1, ddr_regs + AR71XX_DDR_REG_CONTROL); /* MR write */  in qca956x_ddr_init()
284 	writel(CFG_DDR2_EXT_MODE_VAL1, ddr_regs + AR71XX_DDR_REG_EMR);  in qca956x_ddr_init()
287 	writel(0x2, ddr_regs + AR71XX_DDR_REG_CONTROL); /* EMR write */  in qca956x_ddr_init()
290 	writel(CFG_DDR2_EXT_MODE_VAL2, ddr_regs + AR71XX_DDR_REG_EMR);  in qca956x_ddr_init()
293 	writel(0x2, ddr_regs + AR71XX_DDR_REG_CONTROL); /* EMR write */  in qca956x_ddr_init()
296 	writel(CFG_DDR2_REFRESH_VAL, ddr_regs + AR71XX_DDR_REG_REFRESH);  in qca956x_ddr_init()
299 	writel(tap_val, ddr_regs + AR71XX_DDR_REG_TAP_CTRL0);  in qca956x_ddr_init()
300 	writel(tap_val, ddr_regs + AR71XX_DDR_REG_TAP_CTRL1);  in qca956x_ddr_init()
301 	writel(tap_val, ddr_regs + QCA956X_DDR_REG_TAP_CTRL2);  in qca956x_ddr_init()
302 	writel(tap_val, ddr_regs + QCA956X_DDR_REG_TAP_CTRL3);  in qca956x_ddr_init()