53 	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;  in fixed_sdram()  local
59 	out_be32(&im->sysconf.ddrlaw[0].bar,  in fixed_sdram()
61 	out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));  in fixed_sdram()
62 	out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);  in fixed_sdram()
71 	out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);  in fixed_sdram()
72 	out_be32(&im->ddr.cs_config[0], config);  in fixed_sdram()
75 	out_be32(&im->ddr.cs_config[1], 0);  in fixed_sdram()
76 	out_be32(&im->ddr.cs_config[2], 0);  in fixed_sdram()
77 	out_be32(&im->ddr.cs_config[3], 0);  in fixed_sdram()
79 	out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);  in fixed_sdram()
80 	out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);  in fixed_sdram()
81 	out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);  in fixed_sdram()
82 	out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);  in fixed_sdram()
84 	out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_SDRAM_CFG);  in fixed_sdram()
85 	out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_SDRAM_CFG2);  in fixed_sdram()
87 	out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);  in fixed_sdram()
88 	out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE_2);  in fixed_sdram()
90 	out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);  in fixed_sdram()
91 	out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);  in fixed_sdram()
96 	setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);  in fixed_sdram()
123 	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;  in dram_init()  local
124 	fsl_lbc_t *lbc = &im->im_lbc;  in dram_init()
127 	if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)  in dram_init()