Lines Matching refs:clr
104 unsigned int set, clr, clr_src_cpu, clr_pll_con0, clr_src_dmc; in board_clock_init() local
160 clr = CORE_RATIO(7) | COREM0_RATIO(7) | COREM1_RATIO(7) | in board_clock_init()
164 clrsetbits_le32(&clk->div_cpu0, clr, set); in board_clock_init()
176 clr = COPY_RATIO(7) | HPM_RATIO(7) | CORES_RATIO(7); in board_clock_init()
179 clrsetbits_le32(&clk->div_cpu1, clr, set); in board_clock_init()
232 clr = ACP_RATIO(7) | ACP_PCLK_RATIO(7) | DPHY_RATIO(7) | in board_clock_init()
249 clrsetbits_le32(&clk->div_dmc0, clr, set); in board_clock_init()
256 clr = G2D_ACP_RATIO(15) | C2C_RATIO(7) | PWI_RATIO(15) | in board_clock_init()
272 clrsetbits_le32(&clk->div_dmc1, clr, set); in board_clock_init()
279 clr = UART0_SEL(15) | UART1_SEL(15) | UART2_SEL(15) | in board_clock_init()
292 clrsetbits_le32(&clk->src_peril0, clr, set); in board_clock_init()
295 clr = UART0_RATIO(15) | UART1_RATIO(15) | UART2_RATIO(15) | in board_clock_init()
305 clrsetbits_le32(&clk->div_peril0, clr, set); in board_clock_init()
311 clr = MMC0_RATIO(15) | MMC0_PRE_RATIO(255) | MMC1_RATIO(15) | in board_clock_init()
324 clrsetbits_le32(&clk->div_fsys1, clr, set); in board_clock_init()
331 clr = MMC2_RATIO(15) | MMC2_PRE_RATIO(255) | MMC3_RATIO(15) | in board_clock_init()
344 clrsetbits_le32(&clk->div_fsys2, clr, set); in board_clock_init()
351 clr = MMC4_RATIO(15) | MMC4_PRE_RATIO(255); in board_clock_init()
360 clrsetbits_le32(&clk->div_fsys3, clr, set); in board_clock_init()