38 	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;  in fixed_sdram()  local
41 	out_be32(&im->sysconf.ddrlaw[0].bar,  in fixed_sdram()
43 	out_be32(&im->sysconf.ddrlaw[0].ar, (LBLAWAR_EN | (msize_log2 - 1)));  in fixed_sdram()
44 	out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);  in fixed_sdram()
55 	out_be32(&im->ddr.csbnds[0].csbnds,  in fixed_sdram()
59 	out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);  in fixed_sdram()
62 	out_be32(&im->ddr.cs_config[1], 0);  in fixed_sdram()
64 	out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);  in fixed_sdram()
65 	out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);  in fixed_sdram()
66 	out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);  in fixed_sdram()
67 	out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);  in fixed_sdram()
68 	out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);  in fixed_sdram()
70 	out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_SDRAM_CFG);  in fixed_sdram()
72 	out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_SDRAM_CFG2);  in fixed_sdram()
73 	out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);  in fixed_sdram()
74 	out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE_2);  in fixed_sdram()
76 	out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);  in fixed_sdram()
80 	setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);  in fixed_sdram()
93 	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;  in dram_init()  local
94 	volatile fsl_lbc_t *lbc = &im->im_lbc;  in dram_init()
97 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)  in dram_init()
119 	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;  in board_early_init_f()  local
120 	volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)im->gpio;  in board_early_init_f()
138 	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;  in hw_watchdog_reset()  local
139 	volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)im->gpio;  in hw_watchdog_reset()