178 	void __iomem *mmio = uc_priv->mmio_base;  in ahci_host_init()  local
186 	cap_save = readl(mmio + HOST_CAP);  in ahci_host_init()
194 	writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL);  in ahci_host_init()
195 	writel(cap_save, mmio + HOST_CAP);  in ahci_host_init()
196 	writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);  in ahci_host_init()
217 	uc_priv->cap = readl(mmio + HOST_CAP);  in ahci_host_init()
218 	uc_priv->port_map = readl(mmio + HOST_PORTS_IMPL);  in ahci_host_init()
233 		uc_priv->port[i].port_mmio = ahci_port_base(mmio, i);  in ahci_host_init()
314 		writel(1 << i, mmio + HOST_IRQ_STAT);  in ahci_host_init()
323 	tmp = readl(mmio + HOST_CTL);  in ahci_host_init()
325 	writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);  in ahci_host_init()
326 	tmp = readl(mmio + HOST_CTL);  in ahci_host_init()
355 	void __iomem *mmio = uc_priv->mmio_base;  in ahci_print_info()  local
360 	vers = readl(mmio + HOST_VERSION);  in ahci_print_info()
362 	cap2 = readl(mmio + HOST_CAP2);  in ahci_print_info()