113 	void __iomem *port_mmio = uc_priv->port[port].port_mmio;  in ahci_link_up()  local
121 		tmp = readl(port_mmio + PORT_SCR_STAT);  in ahci_link_up()
133 static void sunxi_dma_init(void __iomem *port_mmio)  in sunxi_dma_init()  argument
135 	clrsetbits_le32(port_mmio + PORT_P0DMACR, 0x0000ff00, 0x00004400);  in sunxi_dma_init()
181 	void __iomem *port_mmio;  in ahci_host_init()  local
233 		uc_priv->port[i].port_mmio = ahci_port_base(mmio, i);  in ahci_host_init()
234 		port_mmio = (u8 *)uc_priv->port[i].port_mmio;  in ahci_host_init()
237 		tmp = readl(port_mmio + PORT_CMD);  in ahci_host_init()
243 			writel_with_flush(tmp, port_mmio + PORT_CMD);  in ahci_host_init()
252 		sunxi_dma_init(port_mmio);  in ahci_host_init()
258 		cmd = readl(port_mmio + PORT_CMD);  in ahci_host_init()
260 		writel_with_flush(cmd, port_mmio + PORT_CMD);  in ahci_host_init()
272 		tmp = readl(port_mmio + PORT_SCR_ERR);  in ahci_host_init()
274 			writel(tmp, port_mmio + PORT_SCR_ERR);  in ahci_host_init()
280 			tmp = readl(port_mmio + PORT_TFDATA);  in ahci_host_init()
284 			tmp = readl(port_mmio + PORT_SCR_STAT);  in ahci_host_init()
291 		tmp = readl(port_mmio + PORT_SCR_STAT) & PORT_SCR_STAT_DET_MASK;  in ahci_host_init()
304 		tmp = readl(port_mmio + PORT_SCR_ERR);  in ahci_host_init()
306 		writel(tmp, port_mmio + PORT_SCR_ERR);  in ahci_host_init()
309 		tmp = readl(port_mmio + PORT_IRQ_STAT);  in ahci_host_init()
312 			writel(tmp, port_mmio + PORT_IRQ_STAT);  in ahci_host_init()
317 		tmp = readl(port_mmio + PORT_SCR_STAT);  in ahci_host_init()
541 static int wait_spinup(void __iomem *port_mmio)  in wait_spinup()  argument
548 		tf_data = readl(port_mmio + PORT_TFDATA);  in wait_spinup()
559 	void __iomem *port_mmio = pp->port_mmio;  in ahci_port_start()  local
565 	port_status = readl(port_mmio + PORT_SCR_STAT);  in ahci_port_start()
607 	writel_with_flush(dma_addr, port_mmio + PORT_LST_ADDR);  in ahci_port_start()
608 	writel_with_flush(dma_addr >> 32, port_mmio + PORT_LST_ADDR_HI);  in ahci_port_start()
610 	writel_with_flush(dma_addr, port_mmio + PORT_FIS_ADDR);  in ahci_port_start()
611 	writel_with_flush(dma_addr >> 32, port_mmio + PORT_FIS_ADDR_HI);  in ahci_port_start()
614 	sunxi_dma_init(port_mmio);  in ahci_port_start()
619 			  PORT_CMD_START, port_mmio + PORT_CMD);  in ahci_port_start()
627 	return wait_spinup(port_mmio);  in ahci_port_start()
636 	void __iomem *port_mmio = pp->port_mmio;  in ahci_device_data_io()  local
648 	port_status = readl(port_mmio + PORT_SCR_STAT);  in ahci_device_data_io()
663 	writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);  in ahci_device_data_io()
665 	if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,  in ahci_device_data_io()
1115 	void __iomem *port_mmio = pp->port_mmio;  in ata_io_flush()  local
1127 	writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);  in ata_io_flush()
1129 	if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,  in ata_io_flush()