42 	struct socfpga_a10_clk_platdata *plat = dev_get_platdata(clk->dev);  in socfpga_a10_clk_get_upstream()  local
45 	if (plat->clks.count == 0)  in socfpga_a10_clk_get_upstream()
48 	if (plat->clks.count == 1) {  in socfpga_a10_clk_get_upstream()
49 		*upclk = &plat->clks.clks[0];  in socfpga_a10_clk_get_upstream()
53 	if (!plat->ctl_reg) {  in socfpga_a10_clk_get_upstream()
58 	reg = readl(plat->regs + plat->ctl_reg);  in socfpga_a10_clk_get_upstream()
61 	if (plat->type == SOCFPGA_A10_CLK_MAIN_PLL) {  in socfpga_a10_clk_get_upstream()
64 	} else if (plat->type == SOCFPGA_A10_CLK_PER_PLL) {  in socfpga_a10_clk_get_upstream()
77 	*upclk = &plat->clks.clks[reg];  in socfpga_a10_clk_get_upstream()
83 	struct socfpga_a10_clk_platdata *plat = dev_get_platdata(clk->dev);  in socfpga_a10_clk_endisable()  local
87 	if (!enable && plat->gate_reg)  in socfpga_a10_clk_endisable()
88 		clrbits_le32(plat->regs + plat->gate_reg, BIT(plat->gate_bit));  in socfpga_a10_clk_endisable()
101 	if (enable && plat->gate_reg)  in socfpga_a10_clk_endisable()
102 		setbits_le32(plat->regs + plat->gate_reg, BIT(plat->gate_bit));  in socfpga_a10_clk_endisable()
119 	struct socfpga_a10_clk_platdata *plat = dev_get_platdata(clk->dev);  in socfpga_a10_clk_get_rate()  local
130 	if (plat->type == SOCFPGA_A10_CLK_MAIN_PLL) {  in socfpga_a10_clk_get_rate()
131 		reg = readl(plat->regs + plat->ctl_reg + 4);	/* VCO1 */  in socfpga_a10_clk_get_rate()
138 	} else if (plat->type == SOCFPGA_A10_CLK_PER_PLL) {  in socfpga_a10_clk_get_rate()
139 		reg = readl(plat->regs + plat->ctl_reg + 4);	/* VCO1 */  in socfpga_a10_clk_get_rate()
147 		rate /= plat->fix_div;  in socfpga_a10_clk_get_rate()
149 		if (plat->fix_div == 1 && plat->ctl_reg) {  in socfpga_a10_clk_get_rate()
150 			reg = readl(plat->regs + plat->ctl_reg);  in socfpga_a10_clk_get_rate()
155 		if (plat->div_reg) {  in socfpga_a10_clk_get_rate()
156 			reg = readl(plat->regs + plat->div_reg);  in socfpga_a10_clk_get_rate()
157 			reg >>= plat->div_off;  in socfpga_a10_clk_get_rate()
158 			reg &= (1 << plat->div_len) - 1;  in socfpga_a10_clk_get_rate()
159 			if (plat->type == SOCFPGA_A10_CLK_PERIP_CLK)  in socfpga_a10_clk_get_rate()
161 			if (plat->type == SOCFPGA_A10_CLK_GATE_CLK)  in socfpga_a10_clk_get_rate()
189 	struct socfpga_a10_clk_platdata *plat = dev_get_platdata(dev);  in socfpga_a10_handoff_workaround()  local
191 	struct clk_bulk	*bulk = &plat->clks;  in socfpga_a10_handoff_workaround()
273 	struct socfpga_a10_clk_platdata *plat = dev_get_platdata(dev);  in socfpga_a10_clk_probe()  local
277 	clk_get_bulk(dev, &plat->clks);  in socfpga_a10_clk_probe()
284 		if (plat->clks.count == 3)  in socfpga_a10_clk_probe()
285 			plat->type = SOCFPGA_A10_CLK_MAIN_PLL;  in socfpga_a10_clk_probe()
287 			plat->type = SOCFPGA_A10_CLK_PER_PLL;  in socfpga_a10_clk_probe()
290 		plat->type = SOCFPGA_A10_CLK_PERIP_CLK;  in socfpga_a10_clk_probe()
293 		plat->type = SOCFPGA_A10_CLK_GATE_CLK;  in socfpga_a10_clk_probe()
295 		plat->type = SOCFPGA_A10_CLK_UNKNOWN_CLK;  in socfpga_a10_clk_probe()
303 	struct socfpga_a10_clk_platdata *plat = dev_get_platdata(dev);  in socfpga_a10_ofdata_to_platdata()  local
314 		plat->regs = devfdt_get_addr(dev);  in socfpga_a10_ofdata_to_platdata()
324 		plat->ctl_reg = regs;  in socfpga_a10_ofdata_to_platdata()
325 		plat->regs = pplat->regs;  in socfpga_a10_ofdata_to_platdata()
328 	plat->type = SOCFPGA_A10_CLK_UNKNOWN_CLK;  in socfpga_a10_ofdata_to_platdata()
330 	plat->fix_div = dev_read_u32_default(dev, "fixed-divider", 1);  in socfpga_a10_ofdata_to_platdata()
334 		plat->div_reg = divreg[0];  in socfpga_a10_ofdata_to_platdata()
335 		plat->div_len = divreg[2];  in socfpga_a10_ofdata_to_platdata()
336 		plat->div_off = divreg[1];  in socfpga_a10_ofdata_to_platdata()
341 		plat->gate_reg = gatereg[0];  in socfpga_a10_ofdata_to_platdata()
342 		plat->gate_bit = gatereg[1];  in socfpga_a10_ofdata_to_platdata()