855 			      int pll_id)  in pll_get_fref_ck()  argument
863 	selr = readl(priv->base + pll[pll_id].rckxselr);  in pll_get_fref_ck()
866 	refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]);  in pll_get_fref_ck()
878 			  int pll_id)  in pll_get_fvco()  argument
885 	cfgr1 = readl(priv->base + pll[pll_id].pllxcfgr1);  in pll_get_fvco()
886 	fracr = readl(priv->base + pll[pll_id].pllxfracr);  in pll_get_fvco()
891 	refclk = pll_get_fref_ck(priv, pll_id);  in pll_get_fvco()
912 				    int pll_id, int div_id)  in stm32mp1_read_pll_freq()  argument
922 	cfgr2 = readl(priv->base + pll[pll_id].pllxcfgr2);  in stm32mp1_read_pll_freq()
925 	dfout = pll_get_fvco(priv, pll_id) / (divy + 1);  in stm32mp1_read_pll_freq()
1329 static void pll_start(struct stm32mp1_clk_priv *priv, int pll_id)  in pll_start()  argument
1333 	clrsetbits_le32(priv->base + pll[pll_id].pllxcr,  in pll_start()
1339 static int pll_output(struct stm32mp1_clk_priv *priv, int pll_id, int output)  in pll_output()  argument
1342 	u32 pllxcr = priv->base + pll[pll_id].pllxcr;  in pll_output()
1351 		       pll_id, pllxcr, readl(pllxcr));  in pll_output()
1361 static int pll_stop(struct stm32mp1_clk_priv *priv, int pll_id)  in pll_stop()  argument
1364 	u32 pllxcr = priv->base + pll[pll_id].pllxcr;  in pll_stop()
1380 			      int pll_id, u32 *pllcfg)  in pll_config_output()  argument
1392 	writel(value, rcc + pll[pll_id].pllxcfgr2);  in pll_config_output()
1395 static int pll_config(struct stm32mp1_clk_priv *priv, int pll_id,  in pll_config()  argument
1400 	enum stm32mp1_plltype type = pll[pll_id].plltype;  in pll_config()
1406 	src = readl(priv->base + pll[pll_id].rckxselr) & RCC_SELR_SRC_MASK;  in pll_config()
1408 	refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]) /  in pll_config()
1425 	writel(value, rcc + pll[pll_id].pllxcfgr1);  in pll_config()
1431 	       rcc + pll[pll_id].pllxfracr);  in pll_config()
1434 	setbits_le32(rcc + pll[pll_id].pllxfracr,  in pll_config()
1437 	pll_config_output(priv, pll_id, pllcfg);  in pll_config()
1442 static void pll_csg(struct stm32mp1_clk_priv *priv, int pll_id, u32 *csg)  in pll_csg()  argument
1454 	writel(pllxcsg, priv->base + pll[pll_id].pllxcsgr);  in pll_csg()
1456 	setbits_le32(priv->base + pll[pll_id].pllxcr, RCC_PLLNCR_SSCG_CTRL);  in pll_csg()
1460 					int pll_id,  in pll_set_rate()  argument
1469 	enum stm32mp1_plltype type = pll[pll_id].plltype;  in pll_set_rate()
1479 	sprintf(name, "st,pll@%d", pll_id);  in pll_set_rate()
1489 	fck_ref = pll_get_fref_ck(priv, pll_id);  in pll_set_rate()
1516 	pll_stop(priv, pll_id);  in pll_set_rate()
1517 	pll_config(priv, pll_id, pllcfg, fracv);  in pll_set_rate()
1518 	pll_start(priv, pll_id);  in pll_set_rate()
1519 	pll_output(priv, pll_id, pllcfg[PLLCFG_O]);  in pll_set_rate()
1850 			       int pll_id,  in pll_set_output_rate()  argument
1856 	u32 pllxcr = priv->base + pll[pll_id].pllxcr;  in pll_set_output_rate()
1863 	fvco = pll_get_fvco(priv, pll_id);  in pll_set_output_rate()
1876 	clrsetbits_le32(priv->base + pll[pll_id].pllxcfgr2,  in pll_set_output_rate()