Lines Matching refs:hz
313 static ulong px30_i2c_set_clk(struct px30_clk_priv *priv, ulong clk_id, uint hz) in px30_i2c_set_clk() argument
318 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in px30_i2c_set_clk()
441 static ulong px30_i2s_set_clk(struct px30_clk_priv *priv, ulong clk_id, uint hz) in px30_i2s_set_clk() argument
448 rational_best_approximation(hz, clk_src, in px30_i2s_set_clk()
600 static ulong px30_pwm_set_clk(struct px30_clk_priv *priv, ulong clk_id, uint hz) in px30_pwm_set_clk() argument
605 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in px30_pwm_set_clk()
642 static ulong px30_saradc_set_clk(struct px30_clk_priv *priv, uint hz) in px30_saradc_set_clk() argument
647 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz); in px30_saradc_set_clk()
668 static ulong px30_tsadc_set_clk(struct px30_clk_priv *priv, uint hz) in px30_tsadc_set_clk() argument
673 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz); in px30_tsadc_set_clk()
705 static ulong px30_spi_set_clk(struct px30_clk_priv *priv, ulong clk_id, uint hz) in px30_spi_set_clk() argument
710 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in px30_spi_set_clk()
765 static ulong px30_vop_set_clk(struct px30_clk_priv *priv, ulong clk_id, uint hz) in px30_vop_set_clk() argument
774 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in px30_vop_set_clk()
782 if (hz < PX30_VOP_PLL_LIMIT) { in px30_vop_set_clk()
783 src_clk_div = DIV_ROUND_UP(PX30_VOP_PLL_LIMIT, hz); in px30_vop_set_clk()
791 CPLL, hz * src_clk_div); in px30_vop_set_clk()
801 if (npll_hz >= PX30_VOP_PLL_LIMIT && npll_hz >= hz && in px30_vop_set_clk()
802 npll_hz % hz == 0) { in px30_vop_set_clk()
803 src_clk_div = npll_hz / hz; in px30_vop_set_clk()
806 if (hz < PX30_VOP_PLL_LIMIT) { in px30_vop_set_clk()
808 hz); in px30_vop_set_clk()
816 hz * src_clk_div); in px30_vop_set_clk()
863 ulong hz) in px30_bus_set_clk() argument
874 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in px30_bus_set_clk()
882 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in px30_bus_set_clk()
891 DIV_ROUND_UP(px30_bus_get_clk(priv, ACLK_BUS_PRE), hz); in px30_bus_set_clk()
929 ulong hz) in px30_peri_set_clk() argument
934 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in px30_peri_set_clk()
987 ulong hz) in px30_crypto_set_clk() argument
992 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in px30_crypto_set_clk()
1034 ulong hz) in px30_i2s1_mclk_set_clk() argument
1038 if (hz != 12000000) { in px30_i2s1_mclk_set_clk()
1051 static ulong px30_mac_set_clk(struct px30_clk_priv *priv, uint hz) in px30_mac_set_clk() argument
1066 if (!hz) in px30_mac_set_clk()
1067 hz = 50000000; in px30_mac_set_clk()
1069 div = DIV_ROUND_UP(pll_rate, hz) - 1; in px30_mac_set_clk()
1077 static int px30_mac_set_speed_clk(struct px30_clk_priv *priv, uint hz) in px30_mac_set_speed_clk() argument
1081 if (hz != 2500000 && hz != 25000000) { in px30_mac_set_speed_clk()
1082 debug("Unsupported mac speed:%d\n", hz); in px30_mac_set_speed_clk()
1087 ((hz == 2500000) ? 0 : 1) << RMII_CLK_SEL_SHIFT); in px30_mac_set_speed_clk()
1103 enum px30_pll_id pll_id, ulong hz) in px30_clk_set_pll_rate() argument
1107 if (rkclk_set_pll(&cru->pll[pll_id], &cru->mode, pll_id, hz)) in px30_clk_set_pll_rate()
1112 static ulong px30_armclk_set_clk(struct px30_clk_priv *priv, ulong hz) in px30_armclk_set_clk() argument
1118 rate = get_cpu_settings(hz); in px30_armclk_set_clk()
1130 if (old_rate > hz) { in px30_armclk_set_clk()
1131 if (rkclk_set_pll(&cru->pll[APLL], &cru->mode, APLL, hz)) in px30_armclk_set_clk()
1140 } else if (old_rate < hz) { in px30_armclk_set_clk()
1148 if (rkclk_set_pll(&cru->pll[APLL], &cru->mode, APLL, hz)) in px30_armclk_set_clk()
1497 static ulong px30_pclk_pmu_set_pmuclk(struct px30_pmuclk_priv *priv, ulong hz) in px30_pclk_pmu_set_pmuclk() argument
1502 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in px30_pclk_pmu_set_pmuclk()
1519 static ulong px30_pmuclk_set_gpll_rate(struct px30_pmuclk_priv *priv, ulong hz) in px30_pmuclk_set_gpll_rate() argument
1525 if (priv->gpll_hz == hz) in px30_pmuclk_set_gpll_rate()
1528 div = DIV_ROUND_UP(hz, priv->gpll_hz); in px30_pmuclk_set_gpll_rate()
1537 rkclk_set_pll(&pmucru->pll, &pmucru->pmu_mode, GPLL, hz); in px30_pmuclk_set_gpll_rate()