90 				   enum px30_pll_id pll_id);
201 			 enum px30_pll_id pll_id,  in rkclk_set_pll()  argument
227 	rk_clrsetreg(mode, pll_mode_mask[pll_id],  in rkclk_set_pll()
228 		     PLLMUX_FROM_XIN24M << pll_mode_shift[pll_id]);  in rkclk_set_pll()
249 	rk_clrsetreg(mode, pll_mode_mask[pll_id],  in rkclk_set_pll()
250 		     PLLMUX_FROM_PLL << pll_mode_shift[pll_id]);  in rkclk_set_pll()
256 				   enum px30_pll_id pll_id)  in rkclk_pll_get_rate()  argument
262 	shift = pll_mode_shift[pll_id];  in rkclk_pll_get_rate()
263 	mask = pll_mode_mask[pll_id];  in rkclk_pll_get_rate()
1095 				   enum px30_pll_id pll_id)  in px30_clk_get_pll_rate()  argument
1099 	return rkclk_pll_get_rate(&cru->pll[pll_id], &cru->mode, pll_id);  in px30_clk_get_pll_rate()
1103 				   enum px30_pll_id pll_id, ulong hz)  in px30_clk_set_pll_rate()  argument
1107 	if (rkclk_set_pll(&cru->pll[pll_id], &cru->mode, pll_id, hz))  in px30_clk_set_pll_rate()
1109 	return rkclk_pll_get_rate(&cru->pll[pll_id], &cru->mode, pll_id);  in px30_clk_set_pll_rate()