41 static int rkclk_set_pll(struct rk322x_cru *cru, enum rk_clk_id clk_id,  in rkclk_set_pll()  argument
45 	struct rk322x_pll *pll = &cru->pll[pll_id];  in rkclk_set_pll()
79 static void rkclk_init(struct rk322x_cru *cru)  in rkclk_init()  argument
86 	rk_clrsetreg(&cru->cru_mode_con,  in rkclk_init()
92 	rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);  in rkclk_init()
93 	rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);  in rkclk_init()
106 	rk_clrsetreg(&cru->cru_clksel_con[0],  in rkclk_init()
111 	rk_clrsetreg(&cru->cru_clksel_con[1],  in rkclk_init()
129 	rk_clrsetreg(&cru->cru_clksel_con[0],  in rkclk_init()
134 	rk_clrsetreg(&cru->cru_clksel_con[1],  in rkclk_init()
154 	rk_clrsetreg(&cru->cru_clksel_con[10],  in rkclk_init()
163 	rk_clrsetreg(&cru->cru_mode_con,  in rkclk_init()
170 static uint32_t rkclk_pll_get_rate(struct rk322x_cru *cru,  in rkclk_pll_get_rate()  argument
176 	struct rk322x_pll *pll = &cru->pll[pll_id];  in rkclk_pll_get_rate()
188 	con = readl(&cru->cru_mode_con);  in rkclk_pll_get_rate()
210 static ulong rockchip_mmc_get_clk(struct rk322x_cru *cru, uint clk_general_rate,  in rockchip_mmc_get_clk()  argument
221 		con = readl(&cru->cru_clksel_con[11]);  in rockchip_mmc_get_clk()
223 		con = readl(&cru->cru_clksel_con[12]);  in rockchip_mmc_get_clk()
228 		con = readl(&cru->cru_clksel_con[11]);  in rockchip_mmc_get_clk()
240 static ulong rk322x_mac_set_clk(struct rk322x_cru *cru, uint freq)  in rk322x_mac_set_clk()  argument
248 	if (readl(&cru->cru_clksel_con[5]) & BIT(5)) {  in rk322x_mac_set_clk()
252 		u32 con = readl(&cru->cru_clksel_con[5]);  in rk322x_mac_set_clk()
264 			rk_clrsetreg(&cru->cru_clksel_con[5], CLK_MAC_DIV_MASK,  in rk322x_mac_set_clk()
275 static ulong rockchip_mmc_set_clk(struct rk322x_cru *cru, uint clk_general_rate,  in rockchip_mmc_set_clk()  argument
298 		rk_clrsetreg(&cru->cru_clksel_con[11],  in rockchip_mmc_set_clk()
301 		rk_clrsetreg(&cru->cru_clksel_con[12],  in rockchip_mmc_set_clk()
307 		rk_clrsetreg(&cru->cru_clksel_con[11],  in rockchip_mmc_set_clk()
316 	return rockchip_mmc_get_clk(cru, clk_general_rate, periph);  in rockchip_mmc_set_clk()
319 static int rk322x_ddr_set_clk(struct rk322x_cru *cru, unsigned int set_rate)  in rk322x_ddr_set_clk()  argument
340 	rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,  in rk322x_ddr_set_clk()
342 	rkclk_set_pll(cru, CLK_DDR, &dpll_cfg);  in rk322x_ddr_set_clk()
344 	rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,  in rk322x_ddr_set_clk()
354 	gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);  in rk322x_clk_get_rate()
357 		rate = rkclk_pll_get_rate(priv->cru, clk->id);  in rk322x_clk_get_rate()
363 		rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id);  in rk322x_clk_get_rate()
377 	gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);  in rk322x_clk_set_rate()
383 		new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate,  in rk322x_clk_set_rate()
387 		new_rate = rk322x_ddr_set_clk(priv->cru, rate);  in rk322x_clk_set_rate()
390 		new_rate = rk322x_mac_set_clk(priv->cru, rate);  in rk322x_clk_set_rate()
404 	struct rk322x_cru *cru = priv->cru;  in rk322x_gmac_set_parent()  local
412 		rk_clrsetreg(&cru->cru_clksel_con[5], BIT(5), 0);  in rk322x_gmac_set_parent()
422 		rk_clrsetreg(&cru->cru_clksel_con[5], BIT(5), BIT(5));  in rk322x_gmac_set_parent()
433 	struct rk322x_cru *cru = priv->cru;  in rk322x_gmac_extclk_set_parent()  local
443 		rk_clrsetreg(&cru->cru_clksel_con[29], BIT(10), 0);  in rk322x_gmac_extclk_set_parent()
447 		rk_clrsetreg(&cru->cru_clksel_con[29], BIT(10), BIT(10));  in rk322x_gmac_extclk_set_parent()
477 	priv->cru = dev_read_addr_ptr(dev);  in rk322x_clk_ofdata_to_platdata()
486 	rkclk_init(priv->cru);  in rk322x_clk_probe()