Lines Matching refs:port
68 #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port)) argument
69 #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port)) argument
74 #define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port)) argument
95 #define MVPP2_PRS_PORT_LU_MASK(port) (0xff << ((port) * 4)) argument
96 #define MVPP2_PRS_PORT_LU_VAL(port, val) ((val) << ((port) * 4)) argument
97 #define MVPP2_PRS_INIT_OFFS_REG(port) (0x1004 + ((port) & 4)) argument
98 #define MVPP2_PRS_INIT_OFF_MASK(port) (0x3f << (((port) % 4) * 8)) argument
99 #define MVPP2_PRS_INIT_OFF_VAL(port, val) ((val) << (((port) % 4) * 8)) argument
100 #define MVPP2_PRS_MAX_LOOP_REG(port) (0x100c + ((port) & 4)) argument
101 #define MVPP2_PRS_MAX_LOOP_MASK(port) (0xff << (((port) % 4) * 8)) argument
102 #define MVPP2_PRS_MAX_LOOP_VAL(port, val) ((val) << (((port) % 4) * 8)) argument
115 #define MVPP2_CLS_PORT_WAY_MASK(port) (1 << (port)) argument
125 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port) (0x1980 + ((port) * 4)) argument
128 #define MVPP2_CLS_SWFWD_P2HQ_REG(port) (0x19b0 + ((port) * 4)) argument
130 #define MVPP2_CLS_SWFWD_PCTRL_MASK(port) (1 << (port)) argument
235 #define MVPP2_ISR_ENABLE_REG(port) (0x5420 + 4 * (port)) argument
238 #define MVPP2_ISR_RX_TX_CAUSE_REG(port) (0x5480 + 4 * (port)) argument
247 #define MVPP2_ISR_RX_TX_MASK_REG(port) (0x54a0 + 4 * (port)) argument
336 #define MVPP2_TX_PORT_FLUSH_MASK(port) (1 << (port)) argument
484 #define MVPP22_SMI_PHY_ADDR_REG(port) (MVPP22_SMI + 0x04 + \ argument
485 (0x4 * (port)))
859 #define MVPP2_BM_SWF_LONG_POOL(port) 0 argument
1157 int port; member
1276 static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port, in mvpp2_txdesc_dma_addr_set() argument
1280 if (port->priv->hw_version == MVPP21) { in mvpp2_txdesc_dma_addr_set()
1290 static void mvpp2_txdesc_size_set(struct mvpp2_port *port, in mvpp2_txdesc_size_set() argument
1294 if (port->priv->hw_version == MVPP21) in mvpp2_txdesc_size_set()
1300 static void mvpp2_txdesc_txq_set(struct mvpp2_port *port, in mvpp2_txdesc_txq_set() argument
1304 if (port->priv->hw_version == MVPP21) in mvpp2_txdesc_txq_set()
1310 static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port, in mvpp2_txdesc_cmd_set() argument
1314 if (port->priv->hw_version == MVPP21) in mvpp2_txdesc_cmd_set()
1320 static void mvpp2_txdesc_offset_set(struct mvpp2_port *port, in mvpp2_txdesc_offset_set() argument
1324 if (port->priv->hw_version == MVPP21) in mvpp2_txdesc_offset_set()
1330 static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port, in mvpp2_rxdesc_dma_addr_get() argument
1333 if (port->priv->hw_version == MVPP21) in mvpp2_rxdesc_dma_addr_get()
1339 static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port, in mvpp2_rxdesc_cookie_get() argument
1342 if (port->priv->hw_version == MVPP21) in mvpp2_rxdesc_cookie_get()
1348 static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port, in mvpp2_rxdesc_size_get() argument
1351 if (port->priv->hw_version == MVPP21) in mvpp2_rxdesc_size_get()
1357 static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port, in mvpp2_rxdesc_status_get() argument
1360 if (port->priv->hw_version == MVPP21) in mvpp2_rxdesc_status_get()
1374 static inline int mvpp2_egress_port(struct mvpp2_port *port) in mvpp2_egress_port() argument
1376 return MVPP2_MAX_TCONT + port->id; in mvpp2_egress_port()
1380 static inline int mvpp2_txq_phys(int port, int txq) in mvpp2_txq_phys() argument
1382 return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq; in mvpp2_txq_phys()
1473 unsigned int port, bool add) in mvpp2_prs_tcam_port_set() argument
1478 pe->tcam.byte[enable_off] &= ~(1 << port); in mvpp2_prs_tcam_port_set()
1480 pe->tcam.byte[enable_off] |= 1 << port; in mvpp2_prs_tcam_port_set()
1741 static void mvpp2_prs_mac_drop_all_set(struct mvpp2 *priv, int port, bool add) in mvpp2_prs_mac_drop_all_set() argument
1770 mvpp2_prs_tcam_port_set(&pe, port, add); in mvpp2_prs_mac_drop_all_set()
1776 static void mvpp2_prs_mac_promisc_set(struct mvpp2 *priv, int port, bool add) in mvpp2_prs_mac_promisc_set() argument
1811 mvpp2_prs_tcam_port_set(&pe, port, add); in mvpp2_prs_mac_promisc_set()
1817 static void mvpp2_prs_mac_multi_set(struct mvpp2 *priv, int port, int index, in mvpp2_prs_mac_multi_set() argument
1860 mvpp2_prs_tcam_port_set(&pe, port, add); in mvpp2_prs_mac_multi_set()
1866 static void mvpp2_prs_hw_port_init(struct mvpp2 *priv, int port, int lu_first, in mvpp2_prs_hw_port_init() argument
1873 val &= ~MVPP2_PRS_PORT_LU_MASK(port); in mvpp2_prs_hw_port_init()
1874 val |= MVPP2_PRS_PORT_LU_VAL(port, lu_first); in mvpp2_prs_hw_port_init()
1878 val = mvpp2_read(priv, MVPP2_PRS_MAX_LOOP_REG(port)); in mvpp2_prs_hw_port_init()
1879 val &= ~MVPP2_PRS_MAX_LOOP_MASK(port); in mvpp2_prs_hw_port_init()
1880 val |= MVPP2_PRS_MAX_LOOP_VAL(port, lu_max); in mvpp2_prs_hw_port_init()
1881 mvpp2_write(priv, MVPP2_PRS_MAX_LOOP_REG(port), val); in mvpp2_prs_hw_port_init()
1886 val = mvpp2_read(priv, MVPP2_PRS_INIT_OFFS_REG(port)); in mvpp2_prs_hw_port_init()
1887 val &= ~MVPP2_PRS_INIT_OFF_MASK(port); in mvpp2_prs_hw_port_init()
1888 val |= MVPP2_PRS_INIT_OFF_VAL(port, offset); in mvpp2_prs_hw_port_init()
1889 mvpp2_write(priv, MVPP2_PRS_INIT_OFFS_REG(port), val); in mvpp2_prs_hw_port_init()
1896 int port; in mvpp2_prs_def_flow_init() local
1898 for (port = 0; port < MVPP2_MAX_PORTS; port++) { in mvpp2_prs_def_flow_init()
1901 pe.index = MVPP2_PE_FIRST_DEFAULT_FLOW - port; in mvpp2_prs_def_flow_init()
1907 mvpp2_prs_sram_ai_update(&pe, port, MVPP2_PRS_FLOW_ID_MASK); in mvpp2_prs_def_flow_init()
2294 static int mvpp2_prs_mac_da_accept(struct mvpp2 *priv, int port, in mvpp2_prs_mac_da_accept() argument
2303 pe = mvpp2_prs_mac_da_range_find(priv, (1 << port), da, mask, in mvpp2_prs_mac_da_accept()
2338 mvpp2_prs_tcam_port_set(pe, port, add); in mvpp2_prs_mac_da_accept()
2383 static int mvpp2_prs_update_mac_da(struct mvpp2_port *port, const u8 *da) in mvpp2_prs_update_mac_da() argument
2388 err = mvpp2_prs_mac_da_accept(port->priv, port->id, port->dev_addr, in mvpp2_prs_update_mac_da()
2394 err = mvpp2_prs_mac_da_accept(port->priv, port->id, da, true); in mvpp2_prs_update_mac_da()
2399 memcpy(port->dev_addr, da, ETH_ALEN); in mvpp2_prs_update_mac_da()
2405 static int mvpp2_prs_def_flow(struct mvpp2_port *port) in mvpp2_prs_def_flow() argument
2410 pe = mvpp2_prs_flow_find(port->priv, port->id); in mvpp2_prs_def_flow()
2415 tid = mvpp2_prs_tcam_first_free(port->priv, in mvpp2_prs_def_flow()
2429 mvpp2_prs_sram_ai_update(pe, port->id, MVPP2_PRS_FLOW_ID_MASK); in mvpp2_prs_def_flow()
2433 mvpp2_prs_shadow_set(port->priv, pe->index, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_def_flow()
2436 mvpp2_prs_tcam_port_map_set(pe, (1 << port->id)); in mvpp2_prs_def_flow()
2437 mvpp2_prs_hw_write(port->priv, pe); in mvpp2_prs_def_flow()
2495 static void mvpp2_cls_port_config(struct mvpp2_port *port) in mvpp2_cls_port_config() argument
2501 val = mvpp2_read(port->priv, MVPP2_CLS_PORT_WAY_REG); in mvpp2_cls_port_config()
2502 val &= ~MVPP2_CLS_PORT_WAY_MASK(port->id); in mvpp2_cls_port_config()
2503 mvpp2_write(port->priv, MVPP2_CLS_PORT_WAY_REG, val); in mvpp2_cls_port_config()
2508 le.lkpid = port->id; in mvpp2_cls_port_config()
2514 le.data |= port->first_rxq; in mvpp2_cls_port_config()
2520 mvpp2_cls_lookup_write(port->priv, &le); in mvpp2_cls_port_config()
2524 static void mvpp2_cls_oversize_rxq_set(struct mvpp2_port *port) in mvpp2_cls_oversize_rxq_set() argument
2528 mvpp2_write(port->priv, MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port->id), in mvpp2_cls_oversize_rxq_set()
2529 port->first_rxq & MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK); in mvpp2_cls_oversize_rxq_set()
2531 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_P2HQ_REG(port->id), in mvpp2_cls_oversize_rxq_set()
2532 (port->first_rxq >> MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS)); in mvpp2_cls_oversize_rxq_set()
2534 val = mvpp2_read(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG); in mvpp2_cls_oversize_rxq_set()
2535 val |= MVPP2_CLS_SWFWD_PCTRL_MASK(port->id); in mvpp2_cls_oversize_rxq_set()
2536 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG, val); in mvpp2_cls_oversize_rxq_set()
2682 static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port, in mvpp2_rxq_long_pool_set() argument
2689 prxq = port->rxqs[lrxq]->id; in mvpp2_rxq_long_pool_set()
2691 if (port->priv->hw_version == MVPP21) in mvpp2_rxq_long_pool_set()
2696 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); in mvpp2_rxq_long_pool_set()
2699 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); in mvpp2_rxq_long_pool_set()
2720 static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool, in mvpp2_bm_pool_put() argument
2724 if (port->priv->hw_version == MVPP22) { in mvpp2_bm_pool_put()
2736 mvpp2_write(port->priv, MVPP22_BM_ADDR_HIGH_RLS_REG, val); in mvpp2_bm_pool_put()
2744 mvpp2_write(port->priv, MVPP2_BM_VIRT_RLS_REG, buf_phys_addr); in mvpp2_bm_pool_put()
2745 mvpp2_write(port->priv, MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr); in mvpp2_bm_pool_put()
2749 static void mvpp2_pool_refill(struct mvpp2_port *port, u32 bm, in mvpp2_pool_refill() argument
2755 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr); in mvpp2_pool_refill()
2759 static int mvpp2_bm_bufs_add(struct mvpp2_port *port, in mvpp2_bm_bufs_add() argument
2766 netdev_err(port->dev, in mvpp2_bm_bufs_add()
2773 mvpp2_bm_pool_put(port, bm_pool->id, in mvpp2_bm_bufs_add()
2789 mvpp2_bm_pool_use(struct mvpp2_port *port, int pool, enum mvpp2_bm_type type, in mvpp2_bm_pool_use() argument
2792 struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool]; in mvpp2_bm_pool_use()
2796 netdev_err(port->dev, "mixing pool types is forbidden\n"); in mvpp2_bm_pool_use()
2820 port->priv, new_pool); in mvpp2_bm_pool_use()
2825 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num); in mvpp2_bm_pool_use()
2837 static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port) in mvpp2_swf_bm_pool_init() argument
2841 if (!port->pool_long) { in mvpp2_swf_bm_pool_init()
2842 port->pool_long = in mvpp2_swf_bm_pool_init()
2843 mvpp2_bm_pool_use(port, MVPP2_BM_SWF_LONG_POOL(port->id), in mvpp2_swf_bm_pool_init()
2845 port->pkt_size); in mvpp2_swf_bm_pool_init()
2846 if (!port->pool_long) in mvpp2_swf_bm_pool_init()
2849 port->pool_long->port_map |= (1 << port->id); in mvpp2_swf_bm_pool_init()
2852 mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id); in mvpp2_swf_bm_pool_init()
2860 static void mvpp2_port_mii_set(struct mvpp2_port *port) in mvpp2_port_mii_set() argument
2864 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG); in mvpp2_port_mii_set()
2866 switch (port->phy_interface) { in mvpp2_port_mii_set()
2877 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); in mvpp2_port_mii_set()
2880 static void mvpp2_port_fc_adv_enable(struct mvpp2_port *port) in mvpp2_port_fc_adv_enable() argument
2884 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_port_fc_adv_enable()
2886 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_port_fc_adv_enable()
2889 static void mvpp2_port_enable(struct mvpp2_port *port) in mvpp2_port_enable() argument
2893 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); in mvpp2_port_enable()
2896 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); in mvpp2_port_enable()
2899 static void mvpp2_port_disable(struct mvpp2_port *port) in mvpp2_port_disable() argument
2903 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); in mvpp2_port_disable()
2905 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); in mvpp2_port_disable()
2909 static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port) in mvpp2_port_periodic_xon_disable() argument
2913 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) & in mvpp2_port_periodic_xon_disable()
2915 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG); in mvpp2_port_periodic_xon_disable()
2919 static void mvpp2_port_loopback_set(struct mvpp2_port *port) in mvpp2_port_loopback_set() argument
2923 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG); in mvpp2_port_loopback_set()
2925 if (port->speed == 1000) in mvpp2_port_loopback_set()
2930 if (port->phy_interface == PHY_INTERFACE_MODE_SGMII) in mvpp2_port_loopback_set()
2935 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG); in mvpp2_port_loopback_set()
2938 static void mvpp2_port_reset(struct mvpp2_port *port) in mvpp2_port_reset() argument
2942 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) & in mvpp2_port_reset()
2944 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); in mvpp2_port_reset()
2946 while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) & in mvpp2_port_reset()
2952 static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port) in mvpp2_gmac_max_rx_size_set() argument
2956 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); in mvpp2_gmac_max_rx_size_set()
2958 val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) << in mvpp2_gmac_max_rx_size_set()
2960 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); in mvpp2_gmac_max_rx_size_set()
2966 static int gop_gmac_reset(struct mvpp2_port *port, int reset) in gop_gmac_reset() argument
2971 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG); in gop_gmac_reset()
2976 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); in gop_gmac_reset()
2986 static int gop_gpcs_mode_cfg(struct mvpp2_port *port, int en) in gop_gpcs_mode_cfg() argument
2990 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG); in gop_gpcs_mode_cfg()
2996 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); in gop_gpcs_mode_cfg()
3001 static int gop_bypass_clk_cfg(struct mvpp2_port *port, int en) in gop_bypass_clk_cfg() argument
3005 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG); in gop_bypass_clk_cfg()
3011 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); in gop_bypass_clk_cfg()
3016 static void gop_gmac_sgmii2_5_cfg(struct mvpp2_port *port) in gop_gmac_sgmii2_5_cfg() argument
3025 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); in gop_gmac_sgmii2_5_cfg()
3028 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); in gop_gmac_sgmii2_5_cfg()
3031 val = readl(port->base + MVPP2_GMAC_CTRL_4_REG); in gop_gmac_sgmii2_5_cfg()
3037 writel(val, port->base + MVPP2_GMAC_CTRL_4_REG); in gop_gmac_sgmii2_5_cfg()
3039 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); in gop_gmac_sgmii2_5_cfg()
3045 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); in gop_gmac_sgmii2_5_cfg()
3055 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); in gop_gmac_sgmii2_5_cfg()
3058 static void gop_gmac_sgmii_cfg(struct mvpp2_port *port) in gop_gmac_sgmii_cfg() argument
3067 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); in gop_gmac_sgmii_cfg()
3070 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); in gop_gmac_sgmii_cfg()
3073 val = readl(port->base + MVPP2_GMAC_CTRL_4_REG); in gop_gmac_sgmii_cfg()
3079 writel(val, port->base + MVPP2_GMAC_CTRL_4_REG); in gop_gmac_sgmii_cfg()
3081 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); in gop_gmac_sgmii_cfg()
3084 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); in gop_gmac_sgmii_cfg()
3093 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); in gop_gmac_sgmii_cfg()
3096 static void gop_gmac_rgmii_cfg(struct mvpp2_port *port) in gop_gmac_rgmii_cfg() argument
3105 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); in gop_gmac_rgmii_cfg()
3108 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); in gop_gmac_rgmii_cfg()
3111 val = readl(port->base + MVPP2_GMAC_CTRL_4_REG); in gop_gmac_rgmii_cfg()
3117 writel(val, port->base + MVPP2_GMAC_CTRL_4_REG); in gop_gmac_rgmii_cfg()
3119 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); in gop_gmac_rgmii_cfg()
3122 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); in gop_gmac_rgmii_cfg()
3130 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); in gop_gmac_rgmii_cfg()
3134 static int gop_gmac_mode_cfg(struct mvpp2_port *port) in gop_gmac_mode_cfg() argument
3139 switch (port->phy_interface) { in gop_gmac_mode_cfg()
3141 if (port->phy_speed == 2500) in gop_gmac_mode_cfg()
3142 gop_gmac_sgmii2_5_cfg(port); in gop_gmac_mode_cfg()
3144 gop_gmac_sgmii_cfg(port); in gop_gmac_mode_cfg()
3149 gop_gmac_rgmii_cfg(port); in gop_gmac_mode_cfg()
3157 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); in gop_gmac_mode_cfg()
3160 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); in gop_gmac_mode_cfg()
3163 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG); in gop_gmac_mode_cfg()
3165 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG); in gop_gmac_mode_cfg()
3170 static void gop_xlg_2_gig_mac_cfg(struct mvpp2_port *port) in gop_xlg_2_gig_mac_cfg() argument
3175 if (port->gop_id > 0) in gop_xlg_2_gig_mac_cfg()
3179 val = readl(port->base + MVPP22_XLG_CTRL3_REG); in gop_xlg_2_gig_mac_cfg()
3182 writel(val, port->base + MVPP22_XLG_CTRL3_REG); in gop_xlg_2_gig_mac_cfg()
3185 static int gop_gpcs_reset(struct mvpp2_port *port, int reset) in gop_gpcs_reset() argument
3189 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG); in gop_gpcs_reset()
3194 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); in gop_gpcs_reset()
3200 static int gop_xpcs_mode(struct mvpp2_port *port, int num_of_lanes) in gop_xpcs_mode() argument
3220 val = readl(port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG); in gop_xpcs_mode()
3224 writel(val, port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG); in gop_xpcs_mode()
3229 static int gop_mpcs_mode(struct mvpp2_port *port) in gop_mpcs_mode() argument
3234 val = readl(port->priv->mpcs_base + PCS40G_COMMON_CONTROL); in gop_mpcs_mode()
3236 writel(val, port->priv->mpcs_base + PCS40G_COMMON_CONTROL); in gop_mpcs_mode()
3239 val = readl(port->priv->mpcs_base + PCS_CLOCK_RESET); in gop_mpcs_mode()
3242 writel(val, port->priv->mpcs_base + PCS_CLOCK_RESET); in gop_mpcs_mode()
3248 writel(val, port->priv->mpcs_base + PCS_CLOCK_RESET); in gop_mpcs_mode()
3254 static int gop_xlg_mac_mode_cfg(struct mvpp2_port *port, int num_of_act_lanes) in gop_xlg_mac_mode_cfg() argument
3259 val = readl(port->base + MVPP22_XLG_CTRL0_REG); in gop_xlg_mac_mode_cfg()
3261 writel(val, port->base + MVPP22_XLG_CTRL0_REG); in gop_xlg_mac_mode_cfg()
3263 val = readl(port->base + MVPP22_XLG_CTRL3_REG); in gop_xlg_mac_mode_cfg()
3266 writel(val, port->base + MVPP22_XLG_CTRL3_REG); in gop_xlg_mac_mode_cfg()
3269 val = readl(port->base + MVPP22_XLG_CTRL4_REG); in gop_xlg_mac_mode_cfg()
3274 writel(val, port->base + MVPP22_XLG_CTRL4_REG); in gop_xlg_mac_mode_cfg()
3277 val = readl(port->base + MVPP22_XLG_CTRL1_REG); in gop_xlg_mac_mode_cfg()
3280 writel(val, port->base + MVPP22_XLG_CTRL1_REG); in gop_xlg_mac_mode_cfg()
3283 val = readl(port->base + MVPP22_XLG_INTERRUPT_MASK_REG); in gop_xlg_mac_mode_cfg()
3286 writel(val, port->base + MVPP22_XLG_INTERRUPT_MASK_REG); in gop_xlg_mac_mode_cfg()
3292 static int gop_xpcs_reset(struct mvpp2_port *port, int reset) in gop_xpcs_reset() argument
3297 val = readl(port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG); in gop_xpcs_reset()
3302 writel(val, port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG); in gop_xpcs_reset()
3308 static int gop_xlg_mac_reset(struct mvpp2_port *port, int reset) in gop_xlg_mac_reset() argument
3313 val = readl(port->base + MVPP22_XLG_CTRL0_REG); in gop_xlg_mac_reset()
3318 writel(val, port->base + MVPP22_XLG_CTRL0_REG); in gop_xlg_mac_reset()
3331 static int gop_port_init(struct mvpp2_port *port) in gop_port_init() argument
3333 int mac_num = port->gop_id; in gop_port_init()
3342 switch (port->phy_interface) { in gop_port_init()
3345 gop_gmac_reset(port, 1); in gop_port_init()
3348 gop_gpcs_mode_cfg(port, 0); in gop_port_init()
3349 gop_bypass_clk_cfg(port, 1); in gop_port_init()
3352 gop_gmac_mode_cfg(port); in gop_port_init()
3354 gop_gpcs_reset(port, 0); in gop_port_init()
3357 gop_gmac_reset(port, 0); in gop_port_init()
3362 gop_gpcs_mode_cfg(port, 1); in gop_port_init()
3365 gop_gmac_mode_cfg(port); in gop_port_init()
3367 gop_xlg_2_gig_mac_cfg(port); in gop_port_init()
3370 gop_gpcs_reset(port, 0); in gop_port_init()
3372 gop_gmac_reset(port, 0); in gop_port_init()
3379 gop_xpcs_mode(port, num_of_act_lanes); in gop_port_init()
3380 gop_mpcs_mode(port); in gop_port_init()
3382 gop_xlg_mac_mode_cfg(port, num_of_act_lanes); in gop_port_init()
3385 gop_xpcs_reset(port, 0); in gop_port_init()
3388 gop_xlg_mac_reset(port, 0); in gop_port_init()
3393 __func__, port->phy_interface); in gop_port_init()
3400 static void gop_xlg_mac_port_enable(struct mvpp2_port *port, int enable) in gop_xlg_mac_port_enable() argument
3404 val = readl(port->base + MVPP22_XLG_CTRL0_REG); in gop_xlg_mac_port_enable()
3413 writel(val, port->base + MVPP22_XLG_CTRL0_REG); in gop_xlg_mac_port_enable()
3416 static void gop_port_enable(struct mvpp2_port *port, int enable) in gop_port_enable() argument
3418 switch (port->phy_interface) { in gop_port_enable()
3423 mvpp2_port_enable(port); in gop_port_enable()
3425 mvpp2_port_disable(port); in gop_port_enable()
3429 gop_xlg_mac_port_enable(port, enable); in gop_port_enable()
3434 port->phy_interface); in gop_port_enable()
3677 static void mvpp2_defaults_set(struct mvpp2_port *port) in mvpp2_defaults_set() argument
3681 if (port->priv->hw_version == MVPP21) { in mvpp2_defaults_set()
3683 if (port->flags & MVPP2_F_LOOPBACK) in mvpp2_defaults_set()
3684 mvpp2_port_loopback_set(port); in mvpp2_defaults_set()
3687 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); in mvpp2_defaults_set()
3691 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); in mvpp2_defaults_set()
3695 tx_port_num = mvpp2_egress_port(port); in mvpp2_defaults_set()
3696 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, in mvpp2_defaults_set()
3698 mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0); in mvpp2_defaults_set()
3702 ptxq = mvpp2_txq_phys(port->id, queue); in mvpp2_defaults_set()
3703 mvpp2_write(port->priv, in mvpp2_defaults_set()
3710 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG, 0xc8); in mvpp2_defaults_set()
3711 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG); in mvpp2_defaults_set()
3715 mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val); in mvpp2_defaults_set()
3717 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val); in mvpp2_defaults_set()
3720 mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id), in mvpp2_defaults_set()
3726 queue = port->rxqs[lrxq]->id; in mvpp2_defaults_set()
3727 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); in mvpp2_defaults_set()
3730 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); in mvpp2_defaults_set()
3735 static void mvpp2_ingress_enable(struct mvpp2_port *port) in mvpp2_ingress_enable() argument
3741 queue = port->rxqs[lrxq]->id; in mvpp2_ingress_enable()
3742 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); in mvpp2_ingress_enable()
3744 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); in mvpp2_ingress_enable()
3748 static void mvpp2_ingress_disable(struct mvpp2_port *port) in mvpp2_ingress_disable() argument
3754 queue = port->rxqs[lrxq]->id; in mvpp2_ingress_disable()
3755 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); in mvpp2_ingress_disable()
3757 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); in mvpp2_ingress_disable()
3764 static void mvpp2_egress_enable(struct mvpp2_port *port) in mvpp2_egress_enable() argument
3768 int tx_port_num = mvpp2_egress_port(port); in mvpp2_egress_enable()
3773 struct mvpp2_tx_queue *txq = port->txqs[queue]; in mvpp2_egress_enable()
3779 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_egress_enable()
3780 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap); in mvpp2_egress_enable()
3786 static void mvpp2_egress_disable(struct mvpp2_port *port) in mvpp2_egress_disable() argument
3790 int tx_port_num = mvpp2_egress_port(port); in mvpp2_egress_disable()
3793 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_egress_disable()
3794 reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) & in mvpp2_egress_disable()
3797 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, in mvpp2_egress_disable()
3804 netdev_warn(port->dev, in mvpp2_egress_disable()
3815 reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG); in mvpp2_egress_disable()
3823 mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id) in mvpp2_rxq_received() argument
3825 u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id)); in mvpp2_rxq_received()
3834 mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id, in mvpp2_rxq_status_update() argument
3842 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val); in mvpp2_rxq_status_update()
3857 static void mvpp2_rxq_offset_set(struct mvpp2_port *port, in mvpp2_rxq_offset_set() argument
3865 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); in mvpp2_rxq_offset_set()
3872 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); in mvpp2_rxq_offset_set()
3876 static u32 mvpp2_bm_cookie_build(struct mvpp2_port *port, in mvpp2_bm_cookie_build() argument
3882 pool = (mvpp2_rxdesc_status_get(port, rx_desc) & in mvpp2_bm_cookie_build()
3893 static int mvpp2_txq_pend_desc_num_get(struct mvpp2_port *port, in mvpp2_txq_pend_desc_num_get() argument
3898 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id); in mvpp2_txq_pend_desc_num_get()
3899 val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG); in mvpp2_txq_pend_desc_num_get()
3915 static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending) in mvpp2_aggr_txq_pend_desc_add() argument
3918 mvpp2_write(port->priv, MVPP2_AGGR_TXQ_UPDATE_REG, pending); in mvpp2_aggr_txq_pend_desc_add()
3925 static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port, in mvpp2_txq_sent_desc_proc() argument
3931 val = mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(txq->id)); in mvpp2_txq_sent_desc_proc()
3939 struct mvpp2_port *port = arg; in mvpp2_txq_sent_counter_clear() local
3943 int id = port->txqs[queue]->id; in mvpp2_txq_sent_counter_clear()
3945 mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(id)); in mvpp2_txq_sent_counter_clear()
3950 static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port) in mvpp2_txp_max_tx_size_set() argument
3955 mtu = port->pkt_size * 8; in mvpp2_txp_max_tx_size_set()
3963 tx_port_num = mvpp2_egress_port(port); in mvpp2_txp_max_tx_size_set()
3964 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_txp_max_tx_size_set()
3967 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG); in mvpp2_txp_max_tx_size_set()
3970 mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val); in mvpp2_txp_max_tx_size_set()
3973 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG); in mvpp2_txp_max_tx_size_set()
3979 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val); in mvpp2_txp_max_tx_size_set()
3983 val = mvpp2_read(port->priv, in mvpp2_txp_max_tx_size_set()
3991 mvpp2_write(port->priv, in mvpp2_txp_max_tx_size_set()
3999 static void mvpp2_txq_bufs_free(struct mvpp2_port *port, in mvpp2_txq_bufs_free() argument
4009 static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port, in mvpp2_get_rx_queue() argument
4014 return port->rxqs[queue]; in mvpp2_get_rx_queue()
4017 static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port, in mvpp2_get_tx_queue() argument
4022 return port->txqs[queue]; in mvpp2_get_tx_queue()
4067 static int mvpp2_rxq_init(struct mvpp2_port *port, in mvpp2_rxq_init() argument
4073 rxq->size = port->rx_ring_size; in mvpp2_rxq_init()
4087 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0); in mvpp2_rxq_init()
4090 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id); in mvpp2_rxq_init()
4091 if (port->priv->hw_version == MVPP21) in mvpp2_rxq_init()
4095 mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma); in mvpp2_rxq_init()
4096 mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, rxq->size); in mvpp2_rxq_init()
4097 mvpp2_write(port->priv, MVPP2_RXQ_INDEX_REG, 0); in mvpp2_rxq_init()
4100 mvpp2_rxq_offset_set(port, rxq->id, NET_SKB_PAD); in mvpp2_rxq_init()
4103 mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size); in mvpp2_rxq_init()
4109 static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port, in mvpp2_rxq_drop_pkts() argument
4114 rx_received = mvpp2_rxq_received(port, rxq->id); in mvpp2_rxq_drop_pkts()
4120 u32 bm = mvpp2_bm_cookie_build(port, rx_desc); in mvpp2_rxq_drop_pkts()
4122 mvpp2_pool_refill(port, bm, in mvpp2_rxq_drop_pkts()
4123 mvpp2_rxdesc_dma_addr_get(port, rx_desc), in mvpp2_rxq_drop_pkts()
4124 mvpp2_rxdesc_cookie_get(port, rx_desc)); in mvpp2_rxq_drop_pkts()
4126 mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received); in mvpp2_rxq_drop_pkts()
4130 static void mvpp2_rxq_deinit(struct mvpp2_port *port, in mvpp2_rxq_deinit() argument
4133 mvpp2_rxq_drop_pkts(port, rxq); in mvpp2_rxq_deinit()
4143 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0); in mvpp2_rxq_deinit()
4144 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id); in mvpp2_rxq_deinit()
4145 mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, 0); in mvpp2_rxq_deinit()
4146 mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, 0); in mvpp2_rxq_deinit()
4150 static int mvpp2_txq_init(struct mvpp2_port *port, in mvpp2_txq_init() argument
4157 txq->size = port->tx_ring_size; in mvpp2_txq_init()
4172 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id); in mvpp2_txq_init()
4173 mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, txq->descs_dma); in mvpp2_txq_init()
4174 mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, txq->size & in mvpp2_txq_init()
4176 mvpp2_write(port->priv, MVPP2_TXQ_INDEX_REG, 0); in mvpp2_txq_init()
4177 mvpp2_write(port->priv, MVPP2_TXQ_RSVD_CLR_REG, in mvpp2_txq_init()
4179 val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG); in mvpp2_txq_init()
4181 mvpp2_write(port->priv, MVPP2_TXQ_PENDING_REG, val); in mvpp2_txq_init()
4189 desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) + in mvpp2_txq_init()
4192 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, in mvpp2_txq_init()
4197 tx_port_num = mvpp2_egress_port(port); in mvpp2_txq_init()
4198 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_txq_init()
4200 val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id)); in mvpp2_txq_init()
4204 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val); in mvpp2_txq_init()
4207 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id), in mvpp2_txq_init()
4219 static void mvpp2_txq_deinit(struct mvpp2_port *port, in mvpp2_txq_deinit() argument
4228 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->id), 0); in mvpp2_txq_deinit()
4231 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id); in mvpp2_txq_deinit()
4232 mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, 0); in mvpp2_txq_deinit()
4233 mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, 0); in mvpp2_txq_deinit()
4237 static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq) in mvpp2_txq_clean() argument
4243 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id); in mvpp2_txq_clean()
4244 val = mvpp2_read(port->priv, MVPP2_TXQ_PREF_BUF_REG); in mvpp2_txq_clean()
4246 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val); in mvpp2_txq_clean()
4254 netdev_warn(port->dev, in mvpp2_txq_clean()
4256 port->id, txq->log_id); in mvpp2_txq_clean()
4262 pending = mvpp2_txq_pend_desc_num_get(port, txq); in mvpp2_txq_clean()
4266 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val); in mvpp2_txq_clean()
4272 mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count); in mvpp2_txq_clean()
4282 static void mvpp2_cleanup_txqs(struct mvpp2_port *port) in mvpp2_cleanup_txqs() argument
4288 val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG); in mvpp2_cleanup_txqs()
4291 val |= MVPP2_TX_PORT_FLUSH_MASK(port->id); in mvpp2_cleanup_txqs()
4292 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val); in mvpp2_cleanup_txqs()
4295 txq = port->txqs[queue]; in mvpp2_cleanup_txqs()
4296 mvpp2_txq_clean(port, txq); in mvpp2_cleanup_txqs()
4297 mvpp2_txq_deinit(port, txq); in mvpp2_cleanup_txqs()
4300 mvpp2_txq_sent_counter_clear(port); in mvpp2_cleanup_txqs()
4302 val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id); in mvpp2_cleanup_txqs()
4303 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val); in mvpp2_cleanup_txqs()
4307 static void mvpp2_cleanup_rxqs(struct mvpp2_port *port) in mvpp2_cleanup_rxqs() argument
4312 mvpp2_rxq_deinit(port, port->rxqs[queue]); in mvpp2_cleanup_rxqs()
4316 static int mvpp2_setup_rxqs(struct mvpp2_port *port) in mvpp2_setup_rxqs() argument
4321 err = mvpp2_rxq_init(port, port->rxqs[queue]); in mvpp2_setup_rxqs()
4328 mvpp2_cleanup_rxqs(port); in mvpp2_setup_rxqs()
4333 static int mvpp2_setup_txqs(struct mvpp2_port *port) in mvpp2_setup_txqs() argument
4339 txq = port->txqs[queue]; in mvpp2_setup_txqs()
4340 err = mvpp2_txq_init(port, txq); in mvpp2_setup_txqs()
4345 mvpp2_txq_sent_counter_clear(port); in mvpp2_setup_txqs()
4349 mvpp2_cleanup_txqs(port); in mvpp2_setup_txqs()
4354 static void mvpp2_link_event(struct mvpp2_port *port) in mvpp2_link_event() argument
4356 struct phy_device *phydev = port->phy_dev; in mvpp2_link_event()
4361 if ((port->speed != phydev->speed) || in mvpp2_link_event()
4362 (port->duplex != phydev->duplex)) { in mvpp2_link_event()
4365 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_link_event()
4380 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_link_event()
4382 port->duplex = phydev->duplex; in mvpp2_link_event()
4383 port->speed = phydev->speed; in mvpp2_link_event()
4387 if (phydev->link != port->link) { in mvpp2_link_event()
4389 port->duplex = -1; in mvpp2_link_event()
4390 port->speed = 0; in mvpp2_link_event()
4393 port->link = phydev->link; in mvpp2_link_event()
4399 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_link_event()
4402 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_link_event()
4403 mvpp2_egress_enable(port); in mvpp2_link_event()
4404 mvpp2_ingress_enable(port); in mvpp2_link_event()
4406 mvpp2_ingress_disable(port); in mvpp2_link_event()
4407 mvpp2_egress_disable(port); in mvpp2_link_event()
4415 static void mvpp2_rx_error(struct mvpp2_port *port, in mvpp2_rx_error() argument
4418 u32 status = mvpp2_rxdesc_status_get(port, rx_desc); in mvpp2_rx_error()
4419 size_t sz = mvpp2_rxdesc_size_get(port, rx_desc); in mvpp2_rx_error()
4423 netdev_err(port->dev, "bad rx status %08x (crc error), size=%zu\n", in mvpp2_rx_error()
4427 netdev_err(port->dev, "bad rx status %08x (overrun error), size=%zu\n", in mvpp2_rx_error()
4431 netdev_err(port->dev, "bad rx status %08x (resource error), size=%zu\n", in mvpp2_rx_error()
4438 static int mvpp2_rx_refill(struct mvpp2_port *port, in mvpp2_rx_refill() argument
4442 mvpp2_pool_refill(port, bm, dma_addr, (unsigned long)dma_addr); in mvpp2_rx_refill()
4447 static void mvpp2_start_dev(struct mvpp2_port *port) in mvpp2_start_dev() argument
4449 switch (port->phy_interface) { in mvpp2_start_dev()
4453 mvpp2_gmac_max_rx_size_set(port); in mvpp2_start_dev()
4458 mvpp2_txp_max_tx_size_set(port); in mvpp2_start_dev()
4460 if (port->priv->hw_version == MVPP21) in mvpp2_start_dev()
4461 mvpp2_port_enable(port); in mvpp2_start_dev()
4463 gop_port_enable(port, 1); in mvpp2_start_dev()
4467 static void mvpp2_stop_dev(struct mvpp2_port *port) in mvpp2_stop_dev() argument
4470 mvpp2_ingress_disable(port); in mvpp2_stop_dev()
4472 mvpp2_egress_disable(port); in mvpp2_stop_dev()
4474 if (port->priv->hw_version == MVPP21) in mvpp2_stop_dev()
4475 mvpp2_port_disable(port); in mvpp2_stop_dev()
4477 gop_port_enable(port, 0); in mvpp2_stop_dev()
4480 static void mvpp2_phy_connect(struct udevice *dev, struct mvpp2_port *port) in mvpp2_phy_connect() argument
4484 if (!port->init || port->link == 0) { in mvpp2_phy_connect()
4485 phy_dev = dm_mdio_phy_connect(port->mdio_dev, port->phyaddr, in mvpp2_phy_connect()
4486 dev, port->phy_interface); in mvpp2_phy_connect()
4500 netdev_warn(port->dev, in mvpp2_phy_connect()
4503 port->phyaddr = PHY_MAX_ADDR; in mvpp2_phy_connect()
4504 mvpp2_egress_enable(port); in mvpp2_phy_connect()
4505 mvpp2_ingress_enable(port); in mvpp2_phy_connect()
4510 port->phy_dev = phy_dev; in mvpp2_phy_connect()
4512 netdev_err(port->dev, "cannot connect to phy\n"); in mvpp2_phy_connect()
4518 port->phy_dev = phy_dev; in mvpp2_phy_connect()
4519 port->link = 0; in mvpp2_phy_connect()
4520 port->duplex = 0; in mvpp2_phy_connect()
4521 port->speed = 0; in mvpp2_phy_connect()
4528 port->init = 1; in mvpp2_phy_connect()
4530 mvpp2_egress_enable(port); in mvpp2_phy_connect()
4531 mvpp2_ingress_enable(port); in mvpp2_phy_connect()
4535 static int mvpp2_open(struct udevice *dev, struct mvpp2_port *port) in mvpp2_open() argument
4541 err = mvpp2_prs_mac_da_accept(port->priv, port->id, mac_bcast, true); in mvpp2_open()
4546 err = mvpp2_prs_mac_da_accept(port->priv, port->id, in mvpp2_open()
4547 port->dev_addr, true); in mvpp2_open()
4552 err = mvpp2_prs_def_flow(port); in mvpp2_open()
4559 err = mvpp2_setup_rxqs(port); in mvpp2_open()
4561 netdev_err(port->dev, "cannot allocate Rx queues\n"); in mvpp2_open()
4565 err = mvpp2_setup_txqs(port); in mvpp2_open()
4567 netdev_err(port->dev, "cannot allocate Tx queues\n"); in mvpp2_open()
4571 if (port->phyaddr < PHY_MAX_ADDR) { in mvpp2_open()
4572 mvpp2_phy_connect(dev, port); in mvpp2_open()
4573 mvpp2_link_event(port); in mvpp2_open()
4575 mvpp2_egress_enable(port); in mvpp2_open()
4576 mvpp2_ingress_enable(port); in mvpp2_open()
4579 mvpp2_start_dev(port); in mvpp2_open()
4588 static void mvpp2_port_power_up(struct mvpp2_port *port) in mvpp2_port_power_up() argument
4590 struct mvpp2 *priv = port->priv; in mvpp2_port_power_up()
4594 mvpp2_port_mii_set(port); in mvpp2_port_power_up()
4595 mvpp2_port_periodic_xon_disable(port); in mvpp2_port_power_up()
4597 mvpp2_port_fc_adv_enable(port); in mvpp2_port_power_up()
4598 mvpp2_port_reset(port); in mvpp2_port_power_up()
4602 static int mvpp2_port_init(struct udevice *dev, struct mvpp2_port *port) in mvpp2_port_init() argument
4604 struct mvpp2 *priv = port->priv; in mvpp2_port_init()
4608 if (port->first_rxq + rxq_number > in mvpp2_port_init()
4613 mvpp2_egress_disable(port); in mvpp2_port_init()
4615 mvpp2_port_disable(port); in mvpp2_port_init()
4617 gop_port_enable(port, 0); in mvpp2_port_init()
4619 port->txqs = devm_kcalloc(dev, txq_number, sizeof(*port->txqs), in mvpp2_port_init()
4621 if (!port->txqs) in mvpp2_port_init()
4628 int queue_phy_id = mvpp2_txq_phys(port->id, queue); in mvpp2_port_init()
4648 port->txqs[queue] = txq; in mvpp2_port_init()
4651 port->rxqs = devm_kcalloc(dev, rxq_number, sizeof(*port->rxqs), in mvpp2_port_init()
4653 if (!port->rxqs) in mvpp2_port_init()
4665 rxq->id = port->first_rxq + queue; in mvpp2_port_init()
4666 rxq->port = port->id; in mvpp2_port_init()
4669 port->rxqs[queue] = rxq; in mvpp2_port_init()
4675 struct mvpp2_rx_queue *rxq = port->rxqs[queue]; in mvpp2_port_init()
4677 rxq->size = port->rx_ring_size; in mvpp2_port_init()
4682 mvpp2_ingress_disable(port); in mvpp2_port_init()
4685 mvpp2_defaults_set(port); in mvpp2_port_init()
4688 mvpp2_cls_oversize_rxq_set(port); in mvpp2_port_init()
4689 mvpp2_cls_port_config(port); in mvpp2_port_init()
4692 port->pkt_size = MVPP2_RX_PKT_SIZE(PKTSIZE_ALIGN); in mvpp2_port_init()
4695 err = mvpp2_swf_bm_pool_init(port); in mvpp2_port_init()
4702 static int phy_info_parse(struct udevice *dev, struct mvpp2_port *port) in phy_info_parse() argument
4723 &port->mdio_dev); in phy_info_parse()
4747 &port->phy_reset_gpio, GPIOD_IS_OUT); in phy_info_parse()
4749 &port->phy_tx_disable_gpio, GPIOD_IS_OUT); in phy_info_parse()
4758 port->phy_speed = fdtdec_get_int(gd->fdt_blob, port_node, in phy_info_parse()
4761 port->id = id; in phy_info_parse()
4762 if (port->priv->hw_version == MVPP21) in phy_info_parse()
4763 port->first_rxq = port->id * rxq_number; in phy_info_parse()
4765 port->first_rxq = port->id * port->priv->max_port_rxqs; in phy_info_parse()
4766 port->phy_interface = phy_mode; in phy_info_parse()
4767 port->phyaddr = phyaddr; in phy_info_parse()
4774 static void mvpp2_gpio_init(struct mvpp2_port *port) in mvpp2_gpio_init() argument
4776 if (dm_gpio_is_valid(&port->phy_reset_gpio)) { in mvpp2_gpio_init()
4777 dm_gpio_set_value(&port->phy_reset_gpio, 1); in mvpp2_gpio_init()
4779 dm_gpio_set_value(&port->phy_reset_gpio, 0); in mvpp2_gpio_init()
4782 if (dm_gpio_is_valid(&port->phy_tx_disable_gpio)) in mvpp2_gpio_init()
4783 dm_gpio_set_value(&port->phy_tx_disable_gpio, 0); in mvpp2_gpio_init()
4789 struct mvpp2_port *port, in mvpp2_port_probe() argument
4795 port->tx_ring_size = MVPP2_MAX_TXD; in mvpp2_port_probe()
4796 port->rx_ring_size = MVPP2_MAX_RXD; in mvpp2_port_probe()
4798 err = mvpp2_port_init(dev, port); in mvpp2_port_probe()
4800 dev_err(&pdev->dev, "failed to init port %d\n", port->id); in mvpp2_port_probe()
4803 mvpp2_port_power_up(port); in mvpp2_port_probe()
4806 mvpp2_gpio_init(port); in mvpp2_port_probe()
4809 priv->port_list[port->id] = port; in mvpp2_port_probe()
4850 int port; in mvpp2_rx_fifo_init() local
4852 for (port = 0; port < MVPP2_MAX_PORTS; port++) { in mvpp2_rx_fifo_init()
4854 if (port == 0) { in mvpp2_rx_fifo_init()
4856 MVPP2_RX_DATA_FIFO_SIZE_REG(port), in mvpp2_rx_fifo_init()
4859 MVPP2_RX_ATTR_FIFO_SIZE_REG(port), in mvpp2_rx_fifo_init()
4861 } else if (port == 1) { in mvpp2_rx_fifo_init()
4863 MVPP2_RX_DATA_FIFO_SIZE_REG(port), in mvpp2_rx_fifo_init()
4866 MVPP2_RX_ATTR_FIFO_SIZE_REG(port), in mvpp2_rx_fifo_init()
4870 MVPP2_RX_DATA_FIFO_SIZE_REG(port), in mvpp2_rx_fifo_init()
4873 MVPP2_RX_ATTR_FIFO_SIZE_REG(port), in mvpp2_rx_fifo_init()
4877 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port), in mvpp2_rx_fifo_init()
4879 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port), in mvpp2_rx_fifo_init()
4892 int port, val; in mvpp2_tx_fifo_init() local
4894 for (port = 0; port < MVPP2_MAX_PORTS; port++) { in mvpp2_tx_fifo_init()
4896 if (port == 0) { in mvpp2_tx_fifo_init()
4903 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), val); in mvpp2_tx_fifo_init()
5044 struct mvpp2_port *port = dev_get_priv(dev); in mvpp2_recv() local
5054 if (port->phyaddr < PHY_MAX_ADDR) in mvpp2_recv()
5055 if (!port->phy_dev->link) in mvpp2_recv()
5059 rxq = port->rxqs[0]; in mvpp2_recv()
5062 rx_received = mvpp2_rxq_received(port, rxq->id); in mvpp2_recv()
5069 rx_status = mvpp2_rxdesc_status_get(port, rx_desc); in mvpp2_recv()
5070 rx_bytes = mvpp2_rxdesc_size_get(port, rx_desc); in mvpp2_recv()
5072 dma_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc); in mvpp2_recv()
5074 bm = mvpp2_bm_cookie_build(port, rx_desc); in mvpp2_recv()
5076 bm_pool = &port->priv->bm_pools[pool]; in mvpp2_recv()
5084 mvpp2_rx_error(port, rx_desc); in mvpp2_recv()
5086 mvpp2_pool_refill(port, bm, dma_addr, dma_addr); in mvpp2_recv()
5090 err = mvpp2_rx_refill(port, bm_pool, bm, dma_addr); in mvpp2_recv()
5092 netdev_err(port->dev, "failed to refill BM pools\n"); in mvpp2_recv()
5098 mvpp2_rxq_status_update(port, rxq->id, 1, 1); in mvpp2_recv()
5117 struct mvpp2_port *port = dev_get_priv(dev); in mvpp2_send() local
5123 if (port->phyaddr < PHY_MAX_ADDR) in mvpp2_send()
5124 if (!port->phy_dev->link) in mvpp2_send()
5127 txq = port->txqs[0]; in mvpp2_send()
5128 aggr_txq = &port->priv->aggr_txqs[smp_processor_id()]; in mvpp2_send()
5132 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); in mvpp2_send()
5133 mvpp2_txdesc_size_set(port, tx_desc, length); in mvpp2_send()
5134 mvpp2_txdesc_offset_set(port, tx_desc, in mvpp2_send()
5136 mvpp2_txdesc_dma_addr_set(port, tx_desc, in mvpp2_send()
5139 mvpp2_txdesc_cmd_set(port, tx_desc, in mvpp2_send()
5149 mvpp2_aggr_txq_pend_desc_add(port, 1); in mvpp2_send()
5151 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id); in mvpp2_send()
5159 tx_done = mvpp2_txq_pend_desc_num_get(port, txq); in mvpp2_send()
5168 tx_done = mvpp2_txq_sent_desc_proc(port, txq); in mvpp2_send()
5177 struct mvpp2_port *port = dev_get_priv(dev); in mvpp2_start() local
5180 memcpy(port->dev_addr, pdata->enetaddr, ETH_ALEN); in mvpp2_start()
5183 mvpp2_prs_update_mac_da(port, port->dev_addr); in mvpp2_start()
5185 switch (port->phy_interface) { in mvpp2_start()
5189 mvpp2_port_power_up(port); in mvpp2_start()
5194 mvpp2_open(dev, port); in mvpp2_start()
5201 struct mvpp2_port *port = dev_get_priv(dev); in mvpp2_stop() local
5203 mvpp2_stop_dev(port); in mvpp2_stop()
5204 mvpp2_cleanup_rxqs(port); in mvpp2_stop()
5205 mvpp2_cleanup_txqs(port); in mvpp2_stop()
5210 struct mvpp2_port *port = dev_get_priv(dev); in mvpp2_write_hwaddr() local
5212 return mvpp2_prs_update_mac_da(port, port->dev_addr); in mvpp2_write_hwaddr()
5215 static int mvpp22_smi_phy_addr_cfg(struct mvpp2_port *port) in mvpp22_smi_phy_addr_cfg() argument
5217 writel(port->phyaddr, port->priv->iface_base + in mvpp22_smi_phy_addr_cfg()
5218 MVPP22_SMI_PHY_ADDR_REG(port->gop_id)); in mvpp22_smi_phy_addr_cfg()
5305 struct mvpp2_port *port = dev_get_priv(dev); in mvpp2_probe() local
5313 port->priv = priv; in mvpp2_probe()
5315 err = phy_info_parse(dev, port); in mvpp2_probe()
5326 port->base = (void __iomem *)devfdt_get_addr_index( in mvpp2_probe()
5327 dev->parent, priv_common_regs_num + port->id); in mvpp2_probe()
5328 if (IS_ERR(port->base)) in mvpp2_probe()
5329 return PTR_ERR(port->base); in mvpp2_probe()
5331 port->gop_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), in mvpp2_probe()
5333 if (port->id == -1) { in mvpp2_probe()
5338 port->base = priv->iface_base + MVPP22_PORT_BASE + in mvpp2_probe()
5339 port->gop_id * MVPP22_PORT_OFFSET; in mvpp2_probe()
5342 if (port->phyaddr < PHY_MAX_ADDR) in mvpp2_probe()
5343 mvpp22_smi_phy_addr_cfg(port); in mvpp2_probe()
5346 gop_port_init(port); in mvpp2_probe()
5360 err = mvpp2_port_probe(dev, port, dev_of_offset(dev), priv); in mvpp2_probe()
5365 priv->netc_config |= mvpp2_netc_cfg_create(port->gop_id, in mvpp2_probe()
5366 port->phy_interface); in mvpp2_probe()
5381 struct mvpp2_port *port = dev_get_priv(dev); in mvpp2_remove() local
5382 struct mvpp2 *priv = port->priv; in mvpp2_remove()