Lines Matching refs:hose
72 int fsl_setup_hose(struct pci_controller *hose, unsigned long addr) in fsl_setup_hose() argument
77 memset(hose, 0, sizeof(struct pci_controller)); in fsl_setup_hose()
79 pci_setup_indirect(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); in fsl_setup_hose()
81 return fsl_is_pci_agent(hose); in fsl_setup_hose()
84 static int fsl_pci_setup_inbound_windows(struct pci_controller *hose, in fsl_pci_setup_inbound_windows() argument
88 struct pci_region *r = hose->regions + hose->region_count; in fsl_pci_setup_inbound_windows()
195 hose->region_count = r - hose->regions; in fsl_pci_setup_inbound_windows()
293 void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) in fsl_pci_init() argument
313 struct pci_region *reg = hose->regions + hose->region_count; in fsl_pci_init()
314 pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0); in fsl_pci_init()
323 pci_setup_indirect(hose, cfg_addr, cfg_data); in fsl_pci_init()
327 pci_hose_write_config_dword(hose, dev, 0x440, in fsl_pci_init()
339 for (r = 0; r < hose->region_count; r++) { in fsl_pci_init()
340 unsigned long flags = hose->regions[r].flags; in fsl_pci_init()
341 u32 sz = (__ilog2_u64((u64)hose->regions[r].size) - 1); in fsl_pci_init()
345 u64 start = hose->regions[r].bus_start; in fsl_pci_init()
346 u64 end = start + hose->regions[r].size; in fsl_pci_init()
348 out_be32(&po->powbar, hose->regions[r].phys_start >> 12); in fsl_pci_init()
355 if (hose->regions[r].flags & PCI_REGION_IO) { in fsl_pci_init()
370 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff); in fsl_pci_init()
371 pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pcicsrbar_sz); in fsl_pci_init()
379 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, pcicsrbar); in fsl_pci_init()
387 hose->region_count++; in fsl_pci_init()
390 pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP); in fsl_pci_init()
395 pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap); in fsl_pci_init()
409 inbound = fsl_pci_setup_inbound_windows(hose, in fsl_pci_init()
414 inbound = fsl_pci_setup_inbound_windows(hose, out_lo, pcie_cap, pi); in fsl_pci_init()
417 for (r = 0; r < hose->region_count; r++) in fsl_pci_init()
419 (u64)hose->regions[r].phys_start, in fsl_pci_init()
420 (u64)hose->regions[r].bus_start, in fsl_pci_init()
421 (u64)hose->regions[r].size, in fsl_pci_init()
422 hose->regions[r].flags); in fsl_pci_init()
424 pci_register_hose(hose); in fsl_pci_init()
425 pciauto_config_init(hose); /* grab pci_{mem,prefetch,io} */ in fsl_pci_init()
426 hose->current_busno = hose->first_busno; in fsl_pci_init()
434 pci_hose_read_config_dword(hose, dev, pci_dcr, &temp32); in fsl_pci_init()
436 pci_hose_write_config_dword(hose, dev, pci_dcr, temp32); in fsl_pci_init()
441 pci_hose_read_config_dword(hose, dev, pci_lcr, &temp32); in fsl_pci_init()
443 pci_hose_write_config_dword(hose, dev, pci_lcr, temp32); in fsl_pci_init()
463 pci_hose_read_config_word(hose, dev, PCI_LTSSM, in fsl_pci_init()
471 pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm); in fsl_pci_init()
488 pci_hose_read_config_word(hose, dev, PCI_LTSSM, in fsl_pci_init()
499 pci_hose_write_config_dword(hose, dev, in fsl_pci_init()
520 pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm); in fsl_pci_init()
532 if (fsl_is_pci_agent(hose)) in fsl_pci_init()
536 hose->last_busno = hose->first_busno; in fsl_pci_init()
544 pci_hose_read_config_word(hose, dev, pci_lsr, &temp16); in fsl_pci_init()
548 hose->current_busno++; /* Start scan with secondary */ in fsl_pci_init()
549 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno); in fsl_pci_init()
563 pciauto_setup_device(hose, dev, 0, hose->pci_mem, in fsl_pci_init()
564 hose->pci_prefetch, hose->pci_io); in fsl_pci_init()
567 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &temp16); in fsl_pci_init()
568 pci_hose_write_config_word(hose, dev, PCI_COMMAND, in fsl_pci_init()
573 if (!fsl_is_pci_agent(hose)) { in fsl_pci_init()
575 hose->current_busno); in fsl_pci_init()
576 hose->last_busno = pci_hose_scan_bus(hose, hose->current_busno); in fsl_pci_init()
579 hose->current_busno, temp8); in fsl_pci_init()
580 hose->last_busno = hose->current_busno; in fsl_pci_init()
587 pciauto_postscan_setup_bridge(hose, dev, hose->last_busno); in fsl_pci_init()
590 hose->last_busno = hose->current_busno; in fsl_pci_init()
598 pci_hose_read_config_word(hose, dev, pci_dsr, &temp16); in fsl_pci_init()
600 pci_hose_write_config_word(hose, dev, pci_dsr, 0xffff); in fsl_pci_init()
603 pci_hose_read_config_word (hose, dev, PCI_SEC_STATUS, &temp16); in fsl_pci_init()
605 pci_hose_write_config_word(hose, dev, PCI_SEC_STATUS, 0xffff); in fsl_pci_init()
609 int fsl_is_pci_agent(struct pci_controller *hose) in fsl_is_pci_agent() argument
613 pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0); in fsl_is_pci_agent()
615 pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP); in fsl_is_pci_agent()
616 pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap); in fsl_is_pci_agent()
620 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, in fsl_is_pci_agent()
626 pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prog_if); in fsl_is_pci_agent()
636 struct pci_controller *hose, int busno) in fsl_pci_init_port() argument
655 r = hose->regions + hose->region_count; in fsl_pci_init_port()
671 hose->region_count = r - hose->regions; in fsl_pci_init_port()
672 hose->first_busno = busno; in fsl_pci_init_port()
674 fsl_pci_init(hose, pci_info); in fsl_pci_init_port()
676 if (fsl_is_pci_agent(hose)) { in fsl_pci_init_port()
677 fsl_pci_config_unlock(hose); in fsl_pci_init_port()
678 hose->last_busno = hose->first_busno; in fsl_pci_init_port()
691 pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP); in fsl_pci_init_port()
692 pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap); in fsl_pci_init_port()
695 hose->first_busno, hose->last_busno); in fsl_pci_init_port()
696 return(hose->last_busno + 1); in fsl_pci_init_port()
700 void fsl_pci_config_unlock(struct pci_controller *hose) in fsl_pci_config_unlock() argument
702 pci_dev_t dev = PCI_BDF(hose->first_busno,0,0); in fsl_pci_config_unlock()
707 if (!fsl_is_pci_agent(hose)) in fsl_pci_config_unlock()
710 pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP); in fsl_pci_config_unlock()
711 pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap); in fsl_pci_config_unlock()
713 ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)hose->cfg_addr; in fsl_pci_config_unlock()
719 pci_hose_write_config_byte(hose, dev, in fsl_pci_config_unlock()
723 pci_hose_read_config_word(hose, dev, FSL_PCI_PBFR, &pbfr); in fsl_pci_config_unlock()
725 pci_hose_write_config_word(hose, dev, FSL_PCI_PBFR, pbfr); in fsl_pci_config_unlock()
732 struct pci_controller *hose, in fsl_configure_pcie() argument
740 is_endpoint = fsl_setup_hose(hose, info->regs); in fsl_configure_pcie()
747 return fsl_pci_init_port(info, hose, busno); in fsl_configure_pcie()
820 struct pci_controller *hose; in fsl_pcie_init_ctrl() local
823 hose = calloc(1, sizeof(struct pci_controller)); in fsl_pcie_init_ctrl()
824 if (!hose) in fsl_pcie_init_ctrl()
828 busno = fsl_configure_pcie(pci_info, hose, in fsl_pcie_init_ctrl()
904 struct pci_controller *hose; in ft_fsl_pci_setup() local
906 hose = find_hose_by_cfg_addr((void *)(ctrl_addr)); in ft_fsl_pci_setup()
918 if ((hose == NULL) || (hose->cfg_addr == NULL)) { in ft_fsl_pci_setup()
922 bus_range[1] = hose->last_busno - hose->first_busno; in ft_fsl_pci_setup()
924 fdt_pci_dma_ranges(blob, off, hose); in ft_fsl_pci_setup()