378 void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat)  in cadence_qspi_apb_controller_init()  argument
382 	cadence_qspi_apb_controller_disable(plat->regbase);  in cadence_qspi_apb_controller_init()
385 	reg = readl(plat->regbase + CQSPI_REG_SIZE);  in cadence_qspi_apb_controller_init()
389 	reg |= (plat->page_size << CQSPI_REG_SIZE_PAGE_LSB);  in cadence_qspi_apb_controller_init()
390 	reg |= (plat->block_size << CQSPI_REG_SIZE_BLOCK_LSB);  in cadence_qspi_apb_controller_init()
391 	writel(reg, plat->regbase + CQSPI_REG_SIZE);  in cadence_qspi_apb_controller_init()
394 	writel(0, plat->regbase + CQSPI_REG_REMAP);  in cadence_qspi_apb_controller_init()
397 	writel(plat->fifo_depth / 2, plat->regbase + CQSPI_REG_SRAMPARTITION);  in cadence_qspi_apb_controller_init()
400 	writel(0, plat->regbase + CQSPI_REG_IRQMASK);  in cadence_qspi_apb_controller_init()
402 	cadence_qspi_apb_controller_enable(plat->regbase);  in cadence_qspi_apb_controller_init()
532 int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,  in cadence_qspi_apb_indirect_read_setup()  argument
557 	writel(plat->trigger_address,  in cadence_qspi_apb_indirect_read_setup()
558 	       plat->regbase + CQSPI_REG_INDIRECTTRIGGER);  in cadence_qspi_apb_indirect_read_setup()
569 	writel(addr_value, plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR);  in cadence_qspi_apb_indirect_read_setup()
579 		writel(0x0, plat->regbase + CQSPI_REG_MODE_BIT);  in cadence_qspi_apb_indirect_read_setup()
581 		writel(0xFF, plat->regbase + CQSPI_REG_MODE_BIT);  in cadence_qspi_apb_indirect_read_setup()
594 	writel(rd_reg, plat->regbase + CQSPI_REG_RD_INSTR);  in cadence_qspi_apb_indirect_read_setup()
597 	reg = readl(plat->regbase + CQSPI_REG_SIZE);  in cadence_qspi_apb_indirect_read_setup()
600 	writel(reg, plat->regbase + CQSPI_REG_SIZE);  in cadence_qspi_apb_indirect_read_setup()
604 static u32 cadence_qspi_get_rd_sram_level(struct cadence_spi_platdata *plat)  in cadence_qspi_get_rd_sram_level()  argument
606 	u32 reg = readl(plat->regbase + CQSPI_REG_SDRAMLEVEL);  in cadence_qspi_get_rd_sram_level()
611 static int cadence_qspi_wait_for_data(struct cadence_spi_platdata *plat)  in cadence_qspi_wait_for_data()  argument
617 		reg = cadence_qspi_get_rd_sram_level(plat);  in cadence_qspi_wait_for_data()
626 int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,  in cadence_qspi_apb_indirect_read_execute()  argument
633 	writel(n_rx, plat->regbase + CQSPI_REG_INDIRECTRDBYTES);  in cadence_qspi_apb_indirect_read_execute()
637 	       plat->regbase + CQSPI_REG_INDIRECTRD);  in cadence_qspi_apb_indirect_read_execute()
640 		ret = cadence_qspi_wait_for_data(plat);  in cadence_qspi_apb_indirect_read_execute()
649 			bytes_to_read *= plat->fifo_width;  in cadence_qspi_apb_indirect_read_execute()
657 				readsb(plat->ahbbase, rxbuf, bytes_to_read);  in cadence_qspi_apb_indirect_read_execute()
659 				readsl(plat->ahbbase, rxbuf,  in cadence_qspi_apb_indirect_read_execute()
663 			bytes_to_read = cadence_qspi_get_rd_sram_level(plat);  in cadence_qspi_apb_indirect_read_execute()
668 	ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTRD,  in cadence_qspi_apb_indirect_read_execute()
677 	       plat->regbase + CQSPI_REG_INDIRECTRD);  in cadence_qspi_apb_indirect_read_execute()
684 	       plat->regbase + CQSPI_REG_INDIRECTRD);  in cadence_qspi_apb_indirect_read_execute()
689 int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,  in cadence_qspi_apb_indirect_write_setup()  argument
701 	writel(plat->trigger_address,  in cadence_qspi_apb_indirect_write_setup()
702 	       plat->regbase + CQSPI_REG_INDIRECTTRIGGER);  in cadence_qspi_apb_indirect_write_setup()
710 	writel(reg, plat->regbase + CQSPI_REG_WR_INSTR);  in cadence_qspi_apb_indirect_write_setup()
714 	writel(reg, plat->regbase + CQSPI_REG_INDIRECTWRSTARTADDR);  in cadence_qspi_apb_indirect_write_setup()
716 	reg = readl(plat->regbase + CQSPI_REG_SIZE);  in cadence_qspi_apb_indirect_write_setup()
719 	writel(reg, plat->regbase + CQSPI_REG_SIZE);  in cadence_qspi_apb_indirect_write_setup()
723 int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,  in cadence_qspi_apb_indirect_write_execute()  argument
726 	unsigned int page_size = plat->page_size;  in cadence_qspi_apb_indirect_write_execute()
746 	writel(n_tx, plat->regbase + CQSPI_REG_INDIRECTWRBYTES);  in cadence_qspi_apb_indirect_write_execute()
750 	       plat->regbase + CQSPI_REG_INDIRECTWR);  in cadence_qspi_apb_indirect_write_execute()
754 		writesl(plat->ahbbase, bb_txbuf, write_bytes >> 2);  in cadence_qspi_apb_indirect_write_execute()
756 			writesb(plat->ahbbase,  in cadence_qspi_apb_indirect_write_execute()
760 		ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_SDRAMLEVEL,  in cadence_qspi_apb_indirect_write_execute()
773 	ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTWR,  in cadence_qspi_apb_indirect_write_execute()
782 	       plat->regbase + CQSPI_REG_INDIRECTWR);  in cadence_qspi_apb_indirect_write_execute()
790 	       plat->regbase + CQSPI_REG_INDIRECTWR);  in cadence_qspi_apb_indirect_write_execute()