35 #define reg_write(a, v) writel(v, a)  macro
166 	reg_write(&regs->ctrl, reg_ctrl);  in spi_cfg_mxc()
168 	reg_write(&regs->ctrl, reg_ctrl);  in spi_cfg_mxc()
222 	reg_write(&regs->ctrl, reg_ctrl);  in spi_cfg_mxc()
224 	reg_write(&regs->cfg, reg_config);  in spi_cfg_mxc()
231 	reg_write(&regs->intr, 0);  in spi_cfg_mxc()
232 	reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);  in spi_cfg_mxc()
254 	reg_write(&regs->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN);  in spi_xchg_single()
256 	reg_write(&regs->cfg, mxcs->cfg_reg);  in spi_xchg_single()
260 	reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);  in spi_xchg_single()
277 		reg_write(&regs->txdata, data);  in spi_xchg_single()
298 		reg_write(&regs->txdata, data);  in spi_xchg_single()
303 	reg_write(&regs->ctrl, mxcs->ctrl_reg |  in spi_xchg_single()
318 	reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);  in spi_xchg_single()
401 	reg_write(&regs->rxdata, 1);  in mxc_spi_claim_bus_internal()
408 	reg_write(&regs->period, MXC_CSPIPERIOD_32KHZ);  in mxc_spi_claim_bus_internal()
409 	reg_write(&regs->intr, 0);  in mxc_spi_claim_bus_internal()