Lines Matching refs:rd
24 void TurboAssembler::And(const Register& rd, const Register& rn, in And() argument
27 DCHECK(!rd.IsZero()); in And()
28 LogicalMacro(rd, rn, operand, AND); in And()
31 void TurboAssembler::Ands(const Register& rd, const Register& rn, in Ands() argument
34 DCHECK(!rd.IsZero()); in Ands()
35 LogicalMacro(rd, rn, operand, ANDS); in Ands()
43 void TurboAssembler::Bic(const Register& rd, const Register& rn, in Bic() argument
46 DCHECK(!rd.IsZero()); in Bic()
47 LogicalMacro(rd, rn, operand, BIC); in Bic()
50 void MacroAssembler::Bics(const Register& rd, const Register& rn, in Bics() argument
53 DCHECK(!rd.IsZero()); in Bics()
54 LogicalMacro(rd, rn, operand, BICS); in Bics()
57 void TurboAssembler::Orr(const Register& rd, const Register& rn, in Orr() argument
60 DCHECK(!rd.IsZero()); in Orr()
61 LogicalMacro(rd, rn, operand, ORR); in Orr()
64 void TurboAssembler::Orn(const Register& rd, const Register& rn, in Orn() argument
67 DCHECK(!rd.IsZero()); in Orn()
68 LogicalMacro(rd, rn, operand, ORN); in Orn()
71 void TurboAssembler::Eor(const Register& rd, const Register& rn, in Eor() argument
74 DCHECK(!rd.IsZero()); in Eor()
75 LogicalMacro(rd, rn, operand, EOR); in Eor()
78 void TurboAssembler::Eon(const Register& rd, const Register& rn, in Eon() argument
81 DCHECK(!rd.IsZero()); in Eon()
82 LogicalMacro(rd, rn, operand, EON); in Eon()
114 void TurboAssembler::Add(const Register& rd, const Register& rn, in Add() argument
119 AddSubMacro(rd, rn, -operand.ImmediateValue(), LeaveFlags, SUB); in Add()
121 AddSubMacro(rd, rn, operand, LeaveFlags, ADD); in Add()
125 void TurboAssembler::Adds(const Register& rd, const Register& rn, in Adds() argument
130 AddSubMacro(rd, rn, -operand.ImmediateValue(), SetFlags, SUB); in Adds()
132 AddSubMacro(rd, rn, operand, SetFlags, ADD); in Adds()
136 void TurboAssembler::Sub(const Register& rd, const Register& rn, in Sub() argument
141 AddSubMacro(rd, rn, -operand.ImmediateValue(), LeaveFlags, ADD); in Sub()
143 AddSubMacro(rd, rn, operand, LeaveFlags, SUB); in Sub()
147 void TurboAssembler::Subs(const Register& rd, const Register& rn, in Subs() argument
152 AddSubMacro(rd, rn, -operand.ImmediateValue(), SetFlags, ADD); in Subs()
154 AddSubMacro(rd, rn, operand, SetFlags, SUB); in Subs()
176 void TurboAssembler::Neg(const Register& rd, const Operand& operand) { in Neg() argument
178 DCHECK(!rd.IsZero()); in Neg()
180 Mov(rd, -operand.ImmediateValue()); in Neg()
182 Sub(rd, AppropriateZeroRegFor(rd), operand); in Neg()
186 void TurboAssembler::Negs(const Register& rd, const Operand& operand) { in Negs() argument
188 Subs(rd, AppropriateZeroRegFor(rd), operand); in Negs()
191 void TurboAssembler::Adc(const Register& rd, const Register& rn, in Adc() argument
194 DCHECK(!rd.IsZero()); in Adc()
195 AddSubWithCarryMacro(rd, rn, operand, LeaveFlags, ADC); in Adc()
198 void MacroAssembler::Adcs(const Register& rd, const Register& rn, in Adcs() argument
201 DCHECK(!rd.IsZero()); in Adcs()
202 AddSubWithCarryMacro(rd, rn, operand, SetFlags, ADC); in Adcs()
205 void MacroAssembler::Sbc(const Register& rd, const Register& rn, in Sbc() argument
208 DCHECK(!rd.IsZero()); in Sbc()
209 AddSubWithCarryMacro(rd, rn, operand, LeaveFlags, SBC); in Sbc()
212 void MacroAssembler::Sbcs(const Register& rd, const Register& rn, in Sbcs() argument
215 DCHECK(!rd.IsZero()); in Sbcs()
216 AddSubWithCarryMacro(rd, rn, operand, SetFlags, SBC); in Sbcs()
219 void MacroAssembler::Ngc(const Register& rd, const Operand& operand) { in Ngc() argument
221 DCHECK(!rd.IsZero()); in Ngc()
222 Register zr = AppropriateZeroRegFor(rd); in Ngc()
223 Sbc(rd, zr, operand); in Ngc()
226 void MacroAssembler::Ngcs(const Register& rd, const Operand& operand) { in Ngcs() argument
228 DCHECK(!rd.IsZero()); in Ngcs()
229 Register zr = AppropriateZeroRegFor(rd); in Ngcs()
230 Sbcs(rd, zr, operand); in Ngcs()
233 void TurboAssembler::Mvn(const Register& rd, uint64_t imm) { in Mvn() argument
235 DCHECK(!rd.IsZero()); in Mvn()
236 Mov(rd, ~imm); in Mvn()
273 void TurboAssembler::Asr(const Register& rd, const Register& rn,
276 DCHECK(!rd.IsZero());
277 asr(rd, rn, shift);
280 void TurboAssembler::Asr(const Register& rd, const Register& rn, in Asr() argument
283 DCHECK(!rd.IsZero()); in Asr()
284 asrv(rd, rn, rm); in Asr()
298 void TurboAssembler::Bfi(const Register& rd, const Register& rn, unsigned lsb, in Bfi() argument
301 DCHECK(!rd.IsZero()); in Bfi()
302 bfi(rd, rn, lsb, width); in Bfi()
305 void MacroAssembler::Bfxil(const Register& rd, const Register& rn, unsigned lsb, in Bfxil() argument
308 DCHECK(!rd.IsZero()); in Bfxil()
309 bfxil(rd, rn, lsb, width); in Bfxil()
393 void MacroAssembler::Cinc(const Register& rd, const Register& rn, in Cinc() argument
396 DCHECK(!rd.IsZero()); in Cinc()
398 cinc(rd, rn, cond); in Cinc()
401 void MacroAssembler::Cinv(const Register& rd, const Register& rn, in Cinv() argument
404 DCHECK(!rd.IsZero()); in Cinv()
406 cinv(rd, rn, cond); in Cinv()
409 void TurboAssembler::Cls(const Register& rd, const Register& rn) { in Cls() argument
411 DCHECK(!rd.IsZero()); in Cls()
412 cls(rd, rn); in Cls()
415 void TurboAssembler::Clz(const Register& rd, const Register& rn) { in Clz() argument
417 DCHECK(!rd.IsZero()); in Clz()
418 clz(rd, rn); in Clz()
421 void TurboAssembler::Cneg(const Register& rd, const Register& rn, in Cneg() argument
424 DCHECK(!rd.IsZero()); in Cneg()
426 cneg(rd, rn, cond); in Cneg()
431 void MacroAssembler::CzeroX(const Register& rd, Condition cond) { in CzeroX() argument
433 DCHECK(!rd.IsSP() && rd.Is64Bits()); in CzeroX()
435 csel(rd, xzr, rd, cond); in CzeroX()
440 void TurboAssembler::CmovX(const Register& rd, const Register& rn, in CmovX() argument
443 DCHECK(!rd.IsSP()); in CmovX()
444 DCHECK(rd.Is64Bits() && rn.Is64Bits()); in CmovX()
446 if (rd != rn) { in CmovX()
447 csel(rd, rn, rd, cond); in CmovX()
456 void TurboAssembler::Cset(const Register& rd, Condition cond) { in Cset() argument
458 DCHECK(!rd.IsZero()); in Cset()
460 cset(rd, cond); in Cset()
463 void TurboAssembler::Csetm(const Register& rd, Condition cond) { in Csetm() argument
465 DCHECK(!rd.IsZero()); in Csetm()
467 csetm(rd, cond); in Csetm()
470 void TurboAssembler::Csinc(const Register& rd, const Register& rn, in Csinc() argument
473 DCHECK(!rd.IsZero()); in Csinc()
475 csinc(rd, rn, rm, cond); in Csinc()
478 void MacroAssembler::Csinv(const Register& rd, const Register& rn, in Csinv() argument
481 DCHECK(!rd.IsZero()); in Csinv()
483 csinv(rd, rn, rm, cond); in Csinv()
486 void MacroAssembler::Csneg(const Register& rd, const Register& rn, in Csneg() argument
489 DCHECK(!rd.IsZero()); in Csneg()
491 csneg(rd, rn, rm, cond); in Csneg()
509 void MacroAssembler::Extr(const Register& rd, const Register& rn, in Extr() argument
512 DCHECK(!rd.IsZero()); in Extr()
513 extr(rd, rn, rm, lsb); in Extr()
563 void TurboAssembler::Fcvtas(const Register& rd, const VRegister& fn) { in Fcvtas() argument
565 DCHECK(!rd.IsZero()); in Fcvtas()
566 fcvtas(rd, fn); in Fcvtas()
569 void TurboAssembler::Fcvtau(const Register& rd, const VRegister& fn) { in Fcvtau() argument
571 DCHECK(!rd.IsZero()); in Fcvtau()
572 fcvtau(rd, fn); in Fcvtau()
575 void TurboAssembler::Fcvtms(const Register& rd, const VRegister& fn) { in Fcvtms() argument
577 DCHECK(!rd.IsZero()); in Fcvtms()
578 fcvtms(rd, fn); in Fcvtms()
581 void TurboAssembler::Fcvtmu(const Register& rd, const VRegister& fn) { in Fcvtmu() argument
583 DCHECK(!rd.IsZero()); in Fcvtmu()
584 fcvtmu(rd, fn); in Fcvtmu()
587 void TurboAssembler::Fcvtns(const Register& rd, const VRegister& fn) { in Fcvtns() argument
589 DCHECK(!rd.IsZero()); in Fcvtns()
590 fcvtns(rd, fn); in Fcvtns()
593 void TurboAssembler::Fcvtnu(const Register& rd, const VRegister& fn) { in Fcvtnu() argument
595 DCHECK(!rd.IsZero()); in Fcvtnu()
596 fcvtnu(rd, fn); in Fcvtnu()
599 void TurboAssembler::Fcvtzs(const Register& rd, const VRegister& fn) { in Fcvtzs() argument
601 DCHECK(!rd.IsZero()); in Fcvtzs()
602 fcvtzs(rd, fn); in Fcvtzs()
604 void TurboAssembler::Fcvtzu(const Register& rd, const VRegister& fn) { in Fcvtzu() argument
606 DCHECK(!rd.IsZero()); in Fcvtzu()
607 fcvtzu(rd, fn); in Fcvtzu()
717 void TurboAssembler::Fmov(Register rd, VRegister fn) { in Fmov() argument
719 DCHECK(!rd.IsZero()); in Fmov()
720 fmov(rd, fn); in Fmov()
773 void TurboAssembler::Lsl(const Register& rd, const Register& rn, in Lsl() argument
776 DCHECK(!rd.IsZero()); in Lsl()
777 lsl(rd, rn, shift); in Lsl()
780 void TurboAssembler::Lsl(const Register& rd, const Register& rn, in Lsl() argument
783 DCHECK(!rd.IsZero()); in Lsl()
784 lslv(rd, rn, rm); in Lsl()
787 void TurboAssembler::Lsr(const Register& rd, const Register& rn, in Lsr() argument
790 DCHECK(!rd.IsZero()); in Lsr()
791 lsr(rd, rn, shift); in Lsr()
794 void TurboAssembler::Lsr(const Register& rd, const Register& rn, in Lsr() argument
797 DCHECK(!rd.IsZero()); in Lsr()
798 lsrv(rd, rn, rm); in Lsr()
801 void TurboAssembler::Madd(const Register& rd, const Register& rn, in Madd() argument
804 DCHECK(!rd.IsZero()); in Madd()
805 madd(rd, rn, rm, ra); in Madd()
808 void TurboAssembler::Mneg(const Register& rd, const Register& rn, in Mneg() argument
811 DCHECK(!rd.IsZero()); in Mneg()
812 mneg(rd, rn, rm); in Mneg()
815 void MacroAssembler::Movk(const Register& rd, uint64_t imm, int shift) { in Movk() argument
817 DCHECK(!rd.IsZero()); in Movk()
818 movk(rd, imm, shift); in Movk()
832 void TurboAssembler::Msub(const Register& rd, const Register& rn, in Msub() argument
835 DCHECK(!rd.IsZero()); in Msub()
836 msub(rd, rn, rm, ra); in Msub()
839 void TurboAssembler::Mul(const Register& rd, const Register& rn, in Mul() argument
842 DCHECK(!rd.IsZero()); in Mul()
843 mul(rd, rn, rm); in Mul()
846 void TurboAssembler::Rbit(const Register& rd, const Register& rn) { in Rbit() argument
848 DCHECK(!rd.IsZero()); in Rbit()
849 rbit(rd, rn); in Rbit()
852 void TurboAssembler::Rev(const Register& rd, const Register& rn) { in Rev() argument
854 DCHECK(!rd.IsZero()); in Rev()
855 rev(rd, rn); in Rev()
865 void MacroAssembler::Rev(const Register& rd, const Register& rn) { in Rev() argument
867 DCHECK(!rd.IsZero()); in Rev()
868 rev(rd, rn); in Rev()
871 void TurboAssembler::Rev16(const Register& rd, const Register& rn) { in Rev16() argument
873 DCHECK(!rd.IsZero()); in Rev16()
874 rev16(rd, rn); in Rev16()
877 void TurboAssembler::Rev32(const Register& rd, const Register& rn) { in Rev32() argument
879 DCHECK(!rd.IsZero()); in Rev32()
880 rev32(rd, rn); in Rev32()
883 void TurboAssembler::Ror(const Register& rd, const Register& rs, in Ror() argument
886 DCHECK(!rd.IsZero()); in Ror()
887 ror(rd, rs, shift); in Ror()
890 void TurboAssembler::Ror(const Register& rd, const Register& rn, in Ror() argument
893 DCHECK(!rd.IsZero()); in Ror()
894 rorv(rd, rn, rm); in Ror()
897 void MacroAssembler::Sbfiz(const Register& rd, const Register& rn, unsigned lsb, in Sbfiz() argument
900 DCHECK(!rd.IsZero()); in Sbfiz()
901 sbfiz(rd, rn, lsb, width); in Sbfiz()
904 void TurboAssembler::Sbfx(const Register& rd, const Register& rn, unsigned lsb, in Sbfx() argument
907 DCHECK(!rd.IsZero()); in Sbfx()
908 sbfx(rd, rn, lsb, width); in Sbfx()
917 void TurboAssembler::Sdiv(const Register& rd, const Register& rn, in Sdiv() argument
920 DCHECK(!rd.IsZero()); in Sdiv()
921 sdiv(rd, rn, rm); in Sdiv()
924 void MacroAssembler::Smaddl(const Register& rd, const Register& rn, in Smaddl() argument
927 DCHECK(!rd.IsZero()); in Smaddl()
928 smaddl(rd, rn, rm, ra); in Smaddl()
931 void MacroAssembler::Smsubl(const Register& rd, const Register& rn, in Smsubl() argument
934 DCHECK(!rd.IsZero()); in Smsubl()
935 smsubl(rd, rn, rm, ra); in Smsubl()
938 void TurboAssembler::Smull(const Register& rd, const Register& rn, in Smull() argument
941 DCHECK(!rd.IsZero()); in Smull()
942 smull(rd, rn, rm); in Smull()
945 void MacroAssembler::Smulh(const Register& rd, const Register& rn, in Smulh() argument
948 DCHECK(!rd.IsZero()); in Smulh()
949 smulh(rd, rn, rm); in Smulh()
952 void TurboAssembler::Umull(const Register& rd, const Register& rn, in Umull() argument
955 DCHECK(!rd.IsZero()); in Umull()
956 umaddl(rd, rn, rm, xzr); in Umull()
959 void TurboAssembler::Sxtb(const Register& rd, const Register& rn) { in Sxtb() argument
961 DCHECK(!rd.IsZero()); in Sxtb()
962 sxtb(rd, rn); in Sxtb()
965 void TurboAssembler::Sxth(const Register& rd, const Register& rn) { in Sxth() argument
967 DCHECK(!rd.IsZero()); in Sxth()
968 sxth(rd, rn); in Sxth()
971 void TurboAssembler::Sxtw(const Register& rd, const Register& rn) { in Sxtw() argument
973 DCHECK(!rd.IsZero()); in Sxtw()
974 sxtw(rd, rn); in Sxtw()
977 void TurboAssembler::Ubfiz(const Register& rd, const Register& rn, unsigned lsb, in Ubfiz() argument
980 DCHECK(!rd.IsZero()); in Ubfiz()
981 ubfiz(rd, rn, lsb, width); in Ubfiz()
984 void TurboAssembler::Ubfx(const Register& rd, const Register& rn, unsigned lsb, in Ubfx() argument
987 DCHECK(!rd.IsZero()); in Ubfx()
988 ubfx(rd, rn, lsb, width); in Ubfx()
997 void TurboAssembler::Udiv(const Register& rd, const Register& rn, in Udiv() argument
1000 DCHECK(!rd.IsZero()); in Udiv()
1001 udiv(rd, rn, rm); in Udiv()
1004 void MacroAssembler::Umaddl(const Register& rd, const Register& rn, in Umaddl() argument
1007 DCHECK(!rd.IsZero()); in Umaddl()
1008 umaddl(rd, rn, rm, ra); in Umaddl()
1011 void MacroAssembler::Umsubl(const Register& rd, const Register& rn, in Umsubl() argument
1014 DCHECK(!rd.IsZero()); in Umsubl()
1015 umsubl(rd, rn, rm, ra); in Umsubl()
1018 void TurboAssembler::Uxtb(const Register& rd, const Register& rn) { in Uxtb() argument
1020 DCHECK(!rd.IsZero()); in Uxtb()
1021 uxtb(rd, rn); in Uxtb()
1024 void TurboAssembler::Uxth(const Register& rd, const Register& rn) { in Uxth() argument
1026 DCHECK(!rd.IsZero()); in Uxth()
1027 uxth(rd, rn); in Uxth()
1030 void TurboAssembler::Uxtw(const Register& rd, const Register& rn) { in Uxtw() argument
1032 DCHECK(!rd.IsZero()); in Uxtw()
1033 uxtw(rd, rn); in Uxtw()