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Lines Matching +full:0 +full:v

8 #define SSE2_INSTRUCTION_LIST(V) \  argument
9 V(packsswb, 66, 0F, 63) \
10 V(packssdw, 66, 0F, 6B) \
11 V(packuswb, 66, 0F, 67) \
12 V(pmaddwd, 66, 0F, F5) \
13 V(paddb, 66, 0F, FC) \
14 V(paddw, 66, 0F, FD) \
15 V(paddd, 66, 0F, FE) \
16 V(paddq, 66, 0F, D4) \
17 V(paddsb, 66, 0F, EC) \
18 V(paddsw, 66, 0F, ED) \
19 V(paddusb, 66, 0F, DC) \
20 V(paddusw, 66, 0F, DD) \
21 V(pand, 66, 0F, DB) \
22 V(pcmpeqb, 66, 0F, 74) \
23 V(pcmpeqw, 66, 0F, 75) \
24 V(pcmpeqd, 66, 0F, 76) \
25 V(pcmpgtb, 66, 0F, 64) \
26 V(pcmpgtw, 66, 0F, 65) \
27 V(pcmpgtd, 66, 0F, 66) \
28 V(pmaxsw, 66, 0F, EE) \
29 V(pmaxub, 66, 0F, DE) \
30 V(pminsw, 66, 0F, EA) \
31 V(pminub, 66, 0F, DA) \
32 V(pmullw, 66, 0F, D5) \
33 V(por, 66, 0F, EB) \
34 V(psllw, 66, 0F, F1) \
35 V(pslld, 66, 0F, F2) \
36 V(psllq, 66, 0F, F3) \
37 V(pmuludq, 66, 0F, F4) \
38 V(pavgb, 66, 0F, E0) \
39 V(psraw, 66, 0F, E1) \
40 V(psrad, 66, 0F, E2) \
41 V(pavgw, 66, 0F, E3) \
42 V(psrlw, 66, 0F, D1) \
43 V(psrld, 66, 0F, D2) \
44 V(psrlq, 66, 0F, D3) \
45 V(psubb, 66, 0F, F8) \
46 V(psubw, 66, 0F, F9) \
47 V(psubd, 66, 0F, FA) \
48 V(psubq, 66, 0F, FB) \
49 V(psubsb, 66, 0F, E8) \
50 V(psubsw, 66, 0F, E9) \
51 V(psubusb, 66, 0F, D8) \
52 V(psubusw, 66, 0F, D9) \
53 V(punpcklbw, 66, 0F, 60) \
54 V(punpcklwd, 66, 0F, 61) \
55 V(punpckldq, 66, 0F, 62) \
56 V(punpcklqdq, 66, 0F, 6C) \
57 V(punpckhbw, 66, 0F, 68) \
58 V(punpckhwd, 66, 0F, 69) \
59 V(punpckhdq, 66, 0F, 6A) \
60 V(punpckhqdq, 66, 0F, 6D) \
61 V(pxor, 66, 0F, EF)
63 #define SSSE3_INSTRUCTION_LIST(V) \ argument
64 V(phaddd, 66, 0F, 38, 02) \
65 V(phaddw, 66, 0F, 38, 01) \
66 V(pshufb, 66, 0F, 38, 00) \
67 V(psignb, 66, 0F, 38, 08) \
68 V(psignw, 66, 0F, 38, 09) \
69 V(psignd, 66, 0F, 38, 0A)
72 #define SSSE3_UNOP_INSTRUCTION_LIST(V) \ argument
73 V(pabsb, 66, 0F, 38, 1C) \
74 V(pabsw, 66, 0F, 38, 1D) \
75 V(pabsd, 66, 0F, 38, 1E)
77 #define SSE4_INSTRUCTION_LIST(V) \ argument
78 V(packusdw, 66, 0F, 38, 2B) \
79 V(pminsb, 66, 0F, 38, 38) \
80 V(pminsd, 66, 0F, 38, 39) \
81 V(pminuw, 66, 0F, 38, 3A) \
82 V(pminud, 66, 0F, 38, 3B) \
83 V(pmaxsb, 66, 0F, 38, 3C) \
84 V(pmaxsd, 66, 0F, 38, 3D) \
85 V(pmaxuw, 66, 0F, 38, 3E) \
86 V(pmaxud, 66, 0F, 38, 3F) \
87 V(pmulld, 66, 0F, 38, 40)
89 #define SSE4_RM_INSTRUCTION_LIST(V) \ argument
90 V(pmovsxbw, 66, 0F, 38, 20) \
91 V(pmovsxwd, 66, 0F, 38, 23) \
92 V(pmovsxdq, 66, 0F, 38, 25) \
93 V(pmovzxbw, 66, 0F, 38, 30) \
94 V(pmovzxwd, 66, 0F, 38, 33) \
95 V(pmovzxdq, 66, 0F, 38, 35) \
96 V(ptest, 66, 0F, 38, 17)