157   return block_states_[rpo_number.ToInt()];  in block_state()
185   int ToInt() const {  in ToInt()  function in v8::internal::compiler::RegisterIndex
192       return 1ull << ToInt();  in ToBit()
195       return 3ull << ToInt();  in ToBit()
258     blocks_covered_.Add(block.ToInt());  in AddBlock()
416       int block_rpo = block->rpo_number().ToInt();  in IsLiveAt()
1173   return *register_data_[reg.ToInt()];  in reg_data()
1192     register_data_[reg.ToInt()] = nullptr;  in ResetDataFor()
1199   DCHECK_LT(reg.ToInt(), register_data_.size());  in HasRegisterData()
1200   return register_data_[reg.ToInt()] != nullptr;  in HasRegisterData()
1205     register_data_[reg.ToInt()] = zone()->New<RegisterState::Register>();  in EnsureRegisterData()
1221   register_data_[reg.ToInt()] = source->register_data_[reg.ToInt()];  in CopyFrom()
1225   return register_data_[reg.ToInt()] == other->register_data_[reg.ToInt()];  in Equals()
1553       index_to_float32_reg_code_->at(double_reg.ToInt()) = reg_code;  in SinglePassRegisterAllocator()
1569       index_to_simd128_reg_code_->at(double_reg.ToInt()) = reg_code;  in SinglePassRegisterAllocator()
1828       DCHECK_NE(-1, index_to_float32_reg_code_->at(reg.ToInt()));  in ToRegCode()
1829       return index_to_float32_reg_code_->at(reg.ToInt());  in ToRegCode()
1831       DCHECK_NE(-1, index_to_simd128_reg_code_->at(reg.ToInt()));  in ToRegCode()
1832       return index_to_simd128_reg_code_->at(reg.ToInt());  in ToRegCode()
1836   return index_to_reg_code_[reg.ToInt()];  in ToRegCode()
1949         return index_to_float32_reg_code_->at(reg.ToInt()) != -1;  in IsValidForRep()
1953         return index_to_simd128_reg_code_->at(reg.ToInt()) != -1;  in IsValidForRep()
2582   block_state.dominated_blocks()->Add(block->rpo_number().ToInt());  in InitializeBlockState()
2950           RpoNumber::FromInt(block->loop_end().ToInt() - 1);  in UpdateSpillRangesForLoops()