Lines Matching refs:IsValid
79 VIXL_ASSERT(rm_.IsValid()); in Operand()
87 VIXL_ASSERT(rm_.IsValid()); in Operand()
97 VIXL_ASSERT(rm_.IsValid()); in Operand()
125 VIXL_ASSERT(rm_.IsValid() && rs_.IsValid()); in Operand()
154 bool IsImmediate() const { return !rm_.IsValid(); } in IsImmediate()
157 return rm_.IsValid() && !shift_.IsRRX() && !rs_.IsValid() && (amount_ == 0); in IsPlainRegister()
161 return rm_.IsValid() && !rs_.IsValid(); in IsImmediateShiftedRegister()
165 return rm_.IsValid() && rs_.IsValid(); in IsRegisterShiftedRegister()
400 VIXL_ASSERT(rm_.IsValid()); in NeonOperand()
403 bool IsImmediate() const { return !rm_.IsValid(); } in IsImmediate()
404 bool IsRegister() const { return rm_.IsValid(); } in IsRegister()
529 VIXL_ASSERT(rm_.IsValid()); in QOperand()
587 if (IsValid()) { in ImmediateVand()
618 if (IsValid()) { in ImmediateVorn()
671 VIXL_ASSERT(rn_.IsValid()); in rn_()
688 VIXL_ASSERT(rn_.IsValid()); in rn_()
698 VIXL_ASSERT(rn_.IsValid()); in rn_()
715 VIXL_ASSERT(rn_.IsValid() && rm_.IsValid()); in rn_()
729 VIXL_ASSERT(rn_.IsValid() && rm_.IsValid()); in rn_()
749 VIXL_ASSERT(rn_.IsValid() && rm_.IsValid()); in rn_()
765 VIXL_ASSERT(rn_.IsValid() && rm_.IsValid()); in rn_()
788 VIXL_ASSERT(rn_.IsValid() && rm_.IsValid()); in rn_()
809 VIXL_ASSERT(rn_.IsValid() && rm_.IsValid()); in rn_()
832 bool IsImmediate() const { return !rm_.IsValid(); } in IsImmediate()
833 bool IsImmediateZero() const { return !rm_.IsValid() && (offset_ == 0); } in IsImmediateZero()
835 return rm_.IsValid() && shift_.IsLSL() && (shift_amount_ == 0); in IsPlainRegister()
837 bool IsShiftedRegister() const { return rm_.IsValid(); } in IsShiftedRegister()
839 return (GetAddrMode() == Offset) && !rm_.IsValid(); in IsImmediateOffset()
842 return (GetAddrMode() == Offset) && !rm_.IsValid() && (offset_ == 0); in IsImmediateZeroOffset()
845 return (GetAddrMode() == Offset) && rm_.IsValid() && shift_.IsLSL() && in IsRegisterOffset()
849 return (GetAddrMode() == Offset) && rm_.IsValid(); in IsShiftedRegisterOffset()