1097                     const CPURegister& rt2,  in ldp()  argument
1099   LoadStorePair(rt, rt2, src, LoadPairOpFor(rt, rt2));  in ldp()
1104                     const CPURegister& rt2,  in stp()  argument
1106   LoadStorePair(rt, rt2, dst, StorePairOpFor(rt, rt2));  in stp()
1119                               const CPURegister& rt2,  in LoadStorePair()  argument
1122   VIXL_ASSERT(CPUHas(rt, rt2));  in LoadStorePair()
1125   VIXL_ASSERT(((op & LoadStorePairLBit) == 0) || !rt.Is(rt2));  in LoadStorePair()
1126   VIXL_ASSERT(AreSameSizeAndType(rt, rt2));  in LoadStorePair()
1130   Instr memop = op | Rt(rt) | Rt2(rt2) | RnSP(addr.GetBaseRegister()) |  in LoadStorePair()
1149                      const CPURegister& rt2,  in ldnp()  argument
1151   LoadStorePairNonTemporal(rt, rt2, src, LoadPairNonTemporalOpFor(rt, rt2));  in ldnp()
1156                      const CPURegister& rt2,  in stnp()  argument
1158   LoadStorePairNonTemporal(rt, rt2, dst, StorePairNonTemporalOpFor(rt, rt2));  in stnp()
1163                                          const CPURegister& rt2,  in LoadStorePairNonTemporal()  argument
1166   VIXL_ASSERT(CPUHas(rt, rt2));  in LoadStorePairNonTemporal()
1168   VIXL_ASSERT(!rt.Is(rt2));  in LoadStorePairNonTemporal()
1169   VIXL_ASSERT(AreSameSizeAndType(rt, rt2));  in LoadStorePairNonTemporal()
1176   Emit(op | Rt(rt) | Rt2(rt2) | RnSP(addr.GetBaseRegister()) |  in LoadStorePairNonTemporal()
1436                      const Register& rt2,  in stxp()  argument
1438   VIXL_ASSERT(rt.GetSizeInBits() == rt2.GetSizeInBits());  in stxp()
1441   Emit(op | Rs(rs) | Rt(rt) | Rt2(rt2) | RnSP(dst.GetBaseRegister()));  in stxp()
1446                      const Register& rt2,  in ldxp()  argument
1448   VIXL_ASSERT(rt.GetSizeInBits() == rt2.GetSizeInBits());  in ldxp()
1451   Emit(op | Rs_mask | Rt(rt) | Rt2(rt2) | RnSP(src.GetBaseRegister()));  in ldxp()
1501                       const Register& rt2,  in stlxp()  argument
1503   VIXL_ASSERT(rt.GetSizeInBits() == rt2.GetSizeInBits());  in stlxp()
1506   Emit(op | Rs(rs) | Rt(rt) | Rt2(rt2) | RnSP(dst.GetBaseRegister()));  in stlxp()
1511                       const Register& rt2,  in ldaxp()  argument
1513   VIXL_ASSERT(rt.GetSizeInBits() == rt2.GetSizeInBits());  in ldaxp()
1516   Emit(op | Rs_mask | Rt(rt) | Rt2(rt2) | RnSP(src.GetBaseRegister()));  in ldaxp()
6076                                           const CPURegister& rt2) {  in StorePairOpFor()  argument
6077   VIXL_ASSERT(AreSameSizeAndType(rt, rt2));  in StorePairOpFor()
6078   USE(rt2);  in StorePairOpFor()
6097                                          const CPURegister& rt2) {  in LoadPairOpFor()  argument
6099   return static_cast<LoadStorePairOp>(StorePairOpFor(rt, rt2) |  in LoadPairOpFor()
6105     const CPURegister& rt, const CPURegister& rt2) {  in StorePairNonTemporalOpFor()  argument
6106   VIXL_ASSERT(AreSameSizeAndType(rt, rt2));  in StorePairNonTemporalOpFor()
6107   USE(rt2);  in StorePairNonTemporalOpFor()
6126     const CPURegister& rt, const CPURegister& rt2) {  in LoadPairNonTemporalOpFor()  argument
6129       StorePairNonTemporalOpFor(rt, rt2) | LoadStorePairNonTemporalLBit);  in LoadPairNonTemporalOpFor()
6166 bool Assembler::CPUHas(const CPURegister& rt, const CPURegister& rt2) const {  in CPUHas()
6170   VIXL_ASSERT(AreSameSizeAndType(rt, rt2));  in CPUHas()
6171   USE(rt2);  in CPUHas()