1480   LogicVRegister extendedreg = sxtl2(vform, temp2, src);  in sshll2()
2557 LogicVRegister Simulator::sxtl2(VectorFormat vform,  in sxtl2()  function in vixl::aarch64::Simulator
2913   sxtl2(vform, temp1, src1);  in saddl2()
2914   sxtl2(vform, temp2, src2);  in saddl2()
2936   sxtl2(vform, temp, src2);  in saddw2()
3005   sxtl2(vform, temp1, src1);  in ssubl2()
3006   sxtl2(vform, temp2, src2);  in ssubl2()
3028   sxtl2(vform, temp, src2);  in ssubw2()
3075   sxtl2(vform, temp1, src1);  in sabal2()
3076   sxtl2(vform, temp2, src2);  in sabal2()
3123   sxtl2(vform, temp1, src1);  in sabdl2()
3124   sxtl2(vform, temp2, src2);  in sabdl2()
3171   sxtl2(vform, temp1, src1);  in smull2()
3172   sxtl2(vform, temp2, src2);  in smull2()
3219   sxtl2(vform, temp1, src1);  in smlsl2()
3220   sxtl2(vform, temp2, src2);  in smlsl2()
3267   sxtl2(vform, temp1, src1);  in smlal2()
3268   sxtl2(vform, temp2, src2);  in smlal2()