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RR @!B*ODWC_B @{Ũ_(D@D@( 4 4(44( 5 5(55( 6 6(66( 7 7(77 {!{_{{_&!#%-va_tx_unmute_delayqcom,va-macro            1 1 1 1  1 (1 01 81 1 1 1 1  1 (1 01 81 1 111$1,141<1xx||parmtype=va_tx_unmute_delay:intparm=va_tx_unmute_delay:delay to unmute the tx pathdescription=VA macro driverlicense=GPL v2vermagic=4.14.212-g0bde9a9a6164-ab7264870 SMP preempt mod_unload modversions aarch64name=va_macro_dlkmintree=Ydepends=bolero_cdc_dlkmva-vdd-micb-supplyva_macro_tx_mixer_putva_macro_mclk_eventqcom,va-vdd-micb-currentva_macro_deinitva_macro_initva_macro_tx_mixer_getva_macro_hw_paramsva_macro_enable_micbiasVA_AIF2_CAP MixerVA_AIF1_CAP Mixerva_macro_event_handlerva_macro_get_channel_mapva_macroqcom,va-without-decimationva_macro_put_dec_enumva_macro_dlkmva_macro_mclk_ctrlva_core_clk&va_priv->mclk_lockva_macro_tx_hpf_corner_freq_callbackva_macro_mute_update_callbackregva_macro_validate_dmic_sample_rateqcom,va-dmic-sample-rateVA_AIF2 CaptureVA_AIF1 CaptureVA_DEC7 VolumeVA_DEC6 VolumeVA_DEC5 VolumeVA_DEC4 VolumeVA_DEC3 VolumeVA_DEC2 VolumeVA_DEC1 VolumeVA_DEC0 Volumeva_macro_mclk_enableqcom,va-vdd-micb-voltageva_macro_probeva_macro_enable_dmicva_macro_enable_dectechpack/audio/asoc/codecs/bolero/va-macro.cva-vdd-micbVA DEC7 MUXVA DEC6 MUXVA DEC5 MUXVA DEC4 MUXVA DEC3 MUXVA DEC2 MUXVA DEC1 MUXVA DEC0 MUXVA_AIF2 CAPVA_AIF1 CAPZEROVA_MCLKSWR_MICMSM_DMICva_smic7va_dmic7va_dec7VA SMIC MUX7VA DMIC MUX7VA SWR_MIC7SWR_DMIC7VA DMIC7DEC701234567va_smic6va_dmic6va_dec6VA SMIC MUX6VA DMIC MUX6VA SWR_MIC6SWR_DMIC6VA DMIC6DEC6va_smic5va_dmic5va_dec5VA SMIC MUX5VA DMIC MUX5VA SWR_MIC5SWR_DMIC5VA DMIC5DEC5va_smic4va_dmic4va_dec4VA SMIC MUX4VA DMIC MUX4VA SWR_MIC4SWR_DMIC4VA DMIC4DEC4va_smic3va_dmic3va_dec3VA SMIC MUX3VA DMIC MUX3VA SWR_MIC3SWR_DMIC3VA DMIC3DEC3VA SWR_ADC3va_macro_tx2va_smic2va_dmic2va_dec2VA SMIC MUX2VA DMIC MUX2VA SWR_MIC2SWR_DMIC2VA DMIC2DEC2VA SWR_ADC2va_macro_tx1va_smic1va_dmic1va_dec1VA SMIC MUX1VA DMIC MUX1VA MIC BIAS1VA SWR_MIC1SWR_DMIC1VA DMIC1DEC1VA SWR_ADC1va_smic0va_dmic0va_dec0VA SMIC MUX0VA DMIC MUX0VA SWR_MIC0SWR_DMIC0VA DMIC0DEC0VA SWR_ADC0%s: decimator %u hpf_cut_of_freq 0x%x %s: wname: %s, val: 0x%x %s: set DEC%u rate to %u %s(): widget = %s decimator = %u %s: DMIC_DIV = %u, mclk_rate = %u %s: could not find %s entry in dt %s: could not find %d entry in dt %s: Failed to add widgets %s: Failed to add snd_ctls %s: Failed to add controls %s: Failed to add without dec controls %s: Failed to add routes %s: Invalid DMIC Selection %s:regulator not provided in dtsi %s: decimator %u unmute %s: widget not found %s: e->reg: 0x%x not expected %s: clk get %s failed %s:Looking up %s property in node %s failed %s: ioremap failed %s: register macro failed %s: va request clock en failed %s:va mclk enable failed %s: regulator already disabled %s: clock already disabled %s: invalid DAPM event %d %s: event %d DMIC%d dmic_clk_cnt %d %s: Invalid rate %d, for mclk %d %s: dai_name = %s DAI-ID %x rate %d num_ch %d %s:Failed to get micbias supply for VA Mic %d %s: mclk_enable = %u, dapm = %d clk_users= %d %s: event = %d %s: Setting current failed, err = %d %s: regulator disable failed, err = %d %s: regulator enable failed, err = %d %s: Setting voltage failed, err = %d %s:retry_cnt: %d %s: Invalid TX sample rate: %d %s: Invalid DMIC line on the codec %s: regmap is NULL %s: Invalid AIF %s: priv is null for macro! %s: null device for macro! %s: va_mclk_users is non-zero still, audio SSR fail!! pvg*8U00000000Android (6443078 based on r383902) clang version 11.0.1 (https://android.googlesource.com/toolchain/llvm-project b397f81060ce6d701042b782172ed13bee898b79)va_macro_dlkmMmodule_layout{snd_soc_put_volsw_sxGsnd_soc_get_volsw_sx^snd_soc_info_volsw_sxgTsnd_soc_dapm_get_enum_doublevsnd_soc_info_enum_doublesnd_soc_info_volsw'fparam_ops_intS/snd_soc_dapm_put_enum_doubleVsnd_soc_dapm_mixer_update_power|clear_bit Mset_bitW snd_soc_dapm_kcontrol_widget7Msnd_soc_write uqueue_delayed_work_onӅ3-system_wq__msecs_to_jiffiesqsnd_soc_readGgdcancel_delayed_work_sync/okstrtouintestrpbrkregulator_enableAregulator_set_loadͩregulator_disabledJregulator_set_voltage>լJmutex_unlockfX@regcache_sync_regionuregcache_mark_dirty bolero_request_clock*hhregmap_update_bits_basee8^mutex_lockXzdev_get_regmapGusleep_rangedsnd_soc_update_bitsѣfind_next_bit,EE___ratelimitmsleepTzD__hwasan_load2_noabortUclk_enable wclk_unprepareclk_disableqs|clk_prepare" ^init_timer_keykdelayed_work_timer_fnEimsnd_soc_dapm_sync5@@snd_soc_dapm_ignore_suspend0xsnd_soc_add_codec_controlsJsnd_soc_dapm_new_widgets;snd_soc_dapm_add_routesarsnd_soc_dapm_new_controlss}=F__hwasan_load1_noabortD?bolero_get_device_ptr__dynamic_dev_dbgC/bolero_unregister_macro__stack_chk_failN&݆bolero_register_macrodmemset __mutex_initʍdevm_regulator_getb/of_parse_phandle ddevm_clk_getŃidevm_ioremap__hwasan_store2_noabortdev_errt_A__hwasan_load4_noabort__hwasan_store1_noabortũof_find_property5of_property_read_variable_u32_arrayh'J__hwasan_load8_noabort\__hwasan_store8_noabortdevm_kmalloc__hwasan_store4_noabortg__stack_chk_guardplatform_driver_unregister __platform_driver_registerGNUuNnX d#(F[hv \  dD888" @@< (>R _ qu8( ( L !p8?8`08h8P@88!D98\q8d8N0( !@P8' F(a  4Tp 0 *  hhh28hGh\hqphh@h hhxhhHh+h@ hU hj Pw fh P 0gh !P gh p!P hh !P hhh "P hh  `"P 8ih' "P4 ihB #PO jh] P#Pj jhx #P @kh #P kh @$P lh $P xlh $P lh 0%P  Hmh %P& mh3 %P? (nhL &PX nhe p&Pq nh~ &P `oh 'P oh `'P 0ph 'P ph fH pjh n  q  h- P hB  hW  hl  h  h X h  h  U      $) 7 R  a |        / F N f s           6 P h          , 3 @ N b o ~       '8@Kdq,?Xu$xva_macro_driverva_macro_probeva_macro_validate_dmic_sample_rateva_macro_probe.__keyva_macro_daiva_macro_initva_macro_deinitva_macro_mclk_ctrlva_macro_event_handlerva_macro_remove$dva_macro_validate_dmic_sample_rate.descriptor.21va_macro_validate_dmic_sample_rate.descriptorva_macro_wod_dapm_widgetsva_macro_dapm_widgetsva_audio_mapva_macro_snd_controlsva_macro_tx_hpf_corner_freq_callbackva_macro_mute_update_callbackva_macro_event_handler.descriptorva_macro_event_handler._rsva_macro_get_channel_mapva_macro_hw_paramsva_macro_hw_params.descriptorva_macro_hw_params.descriptor.32va_macro_tx_hpf_corner_freq_callback.descriptorva_macro_mute_update_callback.descriptorva_macro_mclk_eventva_macro_mclk_event.descriptorva_macro_mclk_enableva_macro_mclk_enable.descriptorva_macro_enable_micbiasva_macro_enable_micbias.descriptorva_macro_enable_dmicva_macro_enable_dmic.descriptorva_macro_enable_decva_macro_enable_dec.descriptorva_macro_tx_mixer_getva_macro_tx_mixer_putva_macro_put_dec_enumva_macro_put_dec_enum.descriptor__param_str_va_tx_unmute_delay__param_va_tx_unmute_delay__UNIQUE_ID_va_tx_unmute_delaytype85__UNIQUE_ID_va_tx_unmute_delay86__UNIQUE_ID_description89__UNIQUE_ID_license90va_macro_dt_matchva_macro_dai_opsva_aif1_cap_mixer.compoundliteral.compoundliteral.101.compoundliteral.103.compoundliteral.105.compoundliteral.107.compoundliteral.109.compoundliteral.111.compoundliteral.113va_aif2_cap_mixer.compoundliteral.114.compoundliteral.115.compoundliteral.116.compoundliteral.117.compoundliteral.118.compoundliteral.119.compoundliteral.120.compoundliteral.121va_dmic0_muxva_dmic0_enumva_dmic1_muxva_dmic1_enumva_dmic2_muxva_dmic2_enumva_dmic3_muxva_dmic3_enumva_dmic4_muxva_dmic4_enumva_dmic5_muxva_dmic5_enumva_dmic6_muxva_dmic6_enumva_dmic7_muxva_dmic7_enumva_smic0_muxva_smic0_enumva_smic1_muxva_smic1_enumva_smic2_muxva_smic2_enumva_smic3_muxva_smic3_enumva_smic4_muxva_smic4_enumva_smic5_muxva_smic5_enumva_smic6_muxva_smic6_enumva_smic7_muxva_smic7_enumva_dec0_muxva_dec0_enumva_dec1_muxva_dec1_enumva_dec2_muxva_dec2_enumva_dec3_muxva_dec3_enumva_dec4_muxva_dec4_enumva_dec5_muxva_dec5_enumva_dec6_muxva_dec6_enumva_dec7_muxva_dec7_enumdmic_mux_textsmic_mux_textadc_mux_textdigital_gain.compoundliteral.185.compoundliteral.187.compoundliteral.189.compoundliteral.191.compoundliteral.193.compoundliteral.195.compoundliteral.197.compoundliteral.199__UNIQUE_ID_vermagic59__UNIQUE_ID_name60__UNIQUE_ID_intree61____versions__module_dependsinit_module__this_module__platform_driver_registercleanup_moduleplatform_driver_unregister__stack_chk_guard__hwasan_store4_noabortdevm_kmalloc__hwasan_store8_noabort__hwasan_load8_noabortof_property_read_variable_u32_arrayof_find_property__hwasan_store1_noabort__hwasan_load4_noabortdev_err__hwasan_store2_noabortdevm_ioremapdevm_clk_getof_parse_phandledevm_regulator_get__mutex_initmemsetbolero_register_macro__stack_chk_failbolero_unregister_macro__dynamic_dev_dbgbolero_get_device_ptr__hwasan_load1_noabortsnd_soc_dapm_new_controlssnd_soc_dapm_add_routessnd_soc_dapm_new_widgetssnd_soc_add_codec_controlssnd_soc_dapm_ignore_suspendsnd_soc_dapm_syncdelayed_work_timer_fninit_timer_keyclk_prepareclk_disableclk_unprepare__hwasan_load2_noabortmsleep___ratelimitfind_next_bitsnd_soc_update_bitsusleep_rangedev_get_regmapmutex_lockregmap_update_bits_basebolero_request_clockregcache_mark_dirtyregcache_sync_regionmutex_unlockregulator_set_voltageregulator_disableregulator_set_loadregulator_enablestrpbrkkstrtouintcancel_delayed_work_syncsnd_soc_read__msecs_to_jiffiessystem_wqqueue_delayed_work_onsnd_soc_writesnd_soc_dapm_kcontrol_widgetset_bitclear_bitsnd_soc_dapm_mixer_update_powersnd_soc_dapm_put_enum_doubleparam_ops_intsnd_soc_info_volswsnd_soc_info_enum_doublesnd_soc_dapm_get_enum_doublesnd_soc_info_volsw_sxsnd_soc_get_volsw_sxsnd_soc_put_volsw_sx`| ((0@8@HPX`hpXx(@(tl, " "x 0LXhpt$(,48<DHLPX`l|dddd@ @   2$2,<PXv \`v dp|==pp $0<@DPT X dpt\ x\   T T     =  =(,4`x8% 8% 04tqq  ,@0@<H\d h t|  ff((qq $(048@DHPTX`d`h`ptxqqii ,8D\dp   0 -8 -@ H P UX U` h p x | f f          , 4  8  < V@ VD x         Q  Q $ 0 @ P p |  (     (             ( 0  4  8 < @ T 3 X \ 3 ` h         , D P d l  p  |            $4PX \ hp t x|pG pG 5 508X   ,408<@0DHTh| h$(,h04<l|    ) )(, 0)48 <)Hlt x)| )   $ (,0 4DP\,<Ll  o o  (hxY Y ,4 8 DL P TX\     <HX`ltx | 2 2 $4DT\,`,dtss       o$o(,4<Dp|   (8T`     08<O@DHOLXl|(<Ldx $(,8LTt 0<HT`p    t t H X h t         ! ! !! ! !$!(!D!X!h!t!!!!!!!$"0"8"P<"@"-D"PH"L"-X"`""""""-""-"d0 @X0@PHX 8    0@HP`hpzn8bVJ ('0>@HP`hpzn8bVJ ('0>@HP`hpyv2/ (0@H!P`hp  (l0`@HP`h}pq%uiF F(0@FHyPv`FhpFF2/FFF! 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