1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (c) 2016 Google, Inc 4 */ 5 #ifndef _ASM_ARCH_TIMER_H 6 #define _ASM_ARCH_TIMER_H 7 8 /* Each timer has 4 control bits in ctrl1 register. 9 * Timer1 uses bits 0:3, Timer2 uses bits 4:7 and so on, 10 * such that timer X uses bits (4 * X - 4):(4 * X - 1) 11 * If the timer does not support PWM, bit 4 is reserved. 12 */ 13 #define AST_TMC_EN (1 << 0) 14 #define AST_TMC_1MHZ (1 << 1) 15 #define AST_TMC_OVFINTR (1 << 2) 16 #define AST_TMC_PWM (1 << 3) 17 18 /* Timers are counted from 1 in the datasheet. */ 19 #define AST_TMC_CTRL1_SHIFT(n) (4 * ((n) - 1)) 20 21 #define AST_TMC_RATE (1000*1000) 22 23 #ifndef __ASSEMBLY__ 24 25 /* 26 * All timers share control registers, which makes it harder to make them 27 * separate devices. Since only one timer is needed at the moment, making 28 * it this just one device. 29 */ 30 31 struct ast_timer_counter { 32 u32 status; 33 u32 reload_val; 34 u32 match1; 35 u32 match2; 36 }; 37 38 struct ast_timer { 39 struct ast_timer_counter timers1[3]; 40 u32 ctrl1; 41 u32 ctrl2; 42 #ifdef CONFIG_ASPEED_AST2500 43 u32 ctrl3; 44 u32 ctrl1_clr; 45 #else 46 u32 reserved[2]; 47 #endif 48 struct ast_timer_counter timers2[5]; 49 }; 50 51 #endif /* __ASSEMBLY__ */ 52 53 #endif /* _ASM_ARCH_TIMER_H */ 54