1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Special Function Register (SFR) 4 * 5 * Copyright (C) 2014 Atmel 6 * Bo Shen <voice.shen@atmel.com> 7 */ 8 9 #ifndef __AT91_SFR_H 10 #define __AT91_SFR_H 11 12 struct atmel_sfr { 13 u32 reserved1; /* 0x00 */ 14 union { 15 u32 ddrcfg; /* 0x04: DDR Configuration Register */ 16 u32 ebicsa; /* 0x04: EBI Chip Select Register */ 17 }; 18 u32 reserved2; /* 0x08 */ 19 u32 reserved3; /* 0x0c */ 20 u32 ohciicr; /* 0x10: OHCI Interrupt Configuration Register */ 21 u32 ohciisr; /* 0x14: OHCI Interrupt Status Register */ 22 u32 reserved4[4]; /* 0x18 ~ 0x24 */ 23 u32 secure; /* 0x28: Security Configuration Register */ 24 u32 reserved5[5]; /* 0x2c ~ 0x3c */ 25 u32 ebicfg; /* 0x40: EBI Configuration Register */ 26 u32 reserved6[2]; /* 0x44 ~ 0x48 */ 27 u32 sn0; /* 0x4c */ 28 u32 sn1; /* 0x50 */ 29 u32 aicredir; /* 0x54 */ 30 u32 l2cc_hramc; /* 0x58 */ 31 }; 32 33 /* Register Mapping*/ 34 #define AT91_SFR_DDRCFG 0x04 /* DDR Configuration Register */ 35 #define AT91_SFR_CCFG_EBICSA 0x04 /* EBI Chip Select Register */ 36 /* 0x08 ~ 0x0c: Reserved */ 37 #define AT91_SFR_OHCIICR 0x10 /* OHCI INT Configuration Register */ 38 #define AT91_SFR_OHCIISR 0x14 /* OHCI INT Status Register */ 39 #define AT91_SFR_UTMICKTRIM 0x30 /* UTMI Clock Trimming Register */ 40 #define AT91_SFR_UTMISWAP 0x3c /* UTMI DP/DM Pin Swapping Register */ 41 #define AT91_SFR_LS 0x7c /* Light Sleep Register */ 42 #define AT91_SFR_I2SCLKSEL 0x90 /* I2SC Register */ 43 #define AT91_SFR_WPMR 0xe4 /* Write Protection Mode Register */ 44 45 /* Bit field in DDRCFG */ 46 #define ATMEL_SFR_DDRCFG_FDQIEN 0x00010000 47 #define ATMEL_SFR_DDRCFG_FDQSIEN 0x00020000 48 49 /* Bit field in EBICFG */ 50 #define AT91_SFR_EBICFG_DRIVE0 (0x3 << 0) 51 #define AT91_SFR_EBICFG_DRIVE0_LOW (0x0 << 0) 52 #define AT91_SFR_EBICFG_DRIVE0_MEDIUM (0x2 << 0) 53 #define AT91_SFR_EBICFG_DRIVE0_HIGH (0x3 << 0) 54 #define AT91_SFR_EBICFG_PULL0 (0x3 << 2) 55 #define AT91_SFR_EBICFG_PULL0_UP (0x0 << 2) 56 #define AT91_SFR_EBICFG_PULL0_NONE (0x1 << 2) 57 #define AT91_SFR_EBICFG_PULL0_DOWN (0x3 << 2) 58 #define AT91_SFR_EBICFG_SCH0 (0x1 << 4) 59 #define AT91_SFR_EBICFG_SCH0_OFF (0x0 << 4) 60 #define AT91_SFR_EBICFG_SCH0_ON (0x1 << 4) 61 #define AT91_SFR_EBICFG_DRIVE1 (0x3 << 8) 62 #define AT91_SFR_EBICFG_DRIVE1_LOW (0x0 << 8) 63 #define AT91_SFR_EBICFG_DRIVE1_MEDIUM (0x2 << 8) 64 #define AT91_SFR_EBICFG_DRIVE1_HIGH (0x3 << 8) 65 #define AT91_SFR_EBICFG_PULL1 (0x3 << 10) 66 #define AT91_SFR_EBICFG_PULL1_UP (0x0 << 10) 67 #define AT91_SFR_EBICFG_PULL1_NONE (0x1 << 10) 68 #define AT91_SFR_EBICFG_PULL1_DOWN (0x3 << 10) 69 #define AT91_SFR_EBICFG_SCH1 (0x1 << 12) 70 #define AT91_SFR_EBICFG_SCH1_OFF (0x0 << 12) 71 #define AT91_SFR_EBICFG_SCH1_ON (0x1 << 12) 72 73 /* Bit field in AICREDIR */ 74 #define ATMEL_SFR_AICREDIR_NSAIC 0x00000001 75 76 /* Bit field in DDRCFG */ 77 #define ATMEL_SFR_DDRCFG_FDQIEN 0x00010000 78 #define ATMEL_SFR_DDRCFG_FDQSIEN 0x00020000 79 80 #define AT91_SFR_CCFG_EBI_CSA(cs, val) ((val) << (cs)) 81 #define AT91_SFR_CCFG_EBI_DBPUC BIT(8) 82 #define AT91_SFR_CCFG_EBI_DBPDC BIT(9) 83 #define AT91_SFR_CCFG_EBI_DRIVE_SAM9X60 BIT(16) 84 #define AT91_SFR_CCFG_EBI_DRIVE BIT(17) 85 #define AT91_SFR_CCFG_DQIEN_F BIT(20) 86 #define AT91_SFR_CCFG_NFD0_ON_D16 BIT(24) 87 #define AT91_SFR_CCFG_DDR_MP_EN BIT(25) 88 89 #define AT91_SFR_OHCIICR_RES(x) BIT(x) 90 #define AT91_SFR_OHCIICR_ARIE BIT(4) 91 #define AT91_SFR_OHCIICR_APPSTART BIT(5) 92 #define AT91_SFR_OHCIICR_USB_SUSP(x) BIT(8 + (x)) 93 #define AT91_SFR_OHCIICR_UDPPUDIS BIT(23) 94 #define AT91_OHCIICR_USB_SUSPEND GENMASK(10, 8) 95 96 #define AT91_SFR_OHCIISR_RIS(x) BIT(x) 97 98 #define AT91_UTMICKTRIM_FREQ GENMASK(1, 0) 99 100 #define AT91_SFR_UTMISWAP_PORT(x) BIT(x) 101 102 #define AT91_SFR_LS_VALUE(x) BIT(x) 103 #define AT91_SFR_LS_MEM_POWER_GATING_ULP1_EN BIT(16) 104 105 #define AT91_SFR_WPMR_WPEN BIT(0) 106 #define AT91_SFR_WPMR_WPKEY_MASK GENMASK(31, 8) 107 108 #endif 109