1 /* 2 * Copyright (C) 2018 Marvell International Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * https://spdx.org/licenses 6 */ 7 8 #ifndef MARVELL_DEF_H 9 #define MARVELL_DEF_H 10 11 #include <platform_def.h> 12 13 #include <arch.h> 14 #include <common/tbbr/tbbr_img_def.h> 15 #include <lib/xlat_tables/xlat_tables_v2.h> 16 #include <plat/common/common_def.h> 17 18 /****************************************************************************** 19 * Definitions common to all MARVELL standard platforms 20 *****************************************************************************/ 21 22 /* Special value used to verify platform parameters from BL2 to BL31 */ 23 #define MARVELL_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL 24 25 26 #define MARVELL_CACHE_WRITEBACK_SHIFT 6 27 28 /* 29 * Macros mapping the MPIDR Affinity levels to MARVELL Platform Power levels. 30 * The power levels have a 1:1 mapping with the MPIDR affinity levels. 31 */ 32 #define MARVELL_PWR_LVL0 MPIDR_AFFLVL0 33 #define MARVELL_PWR_LVL1 MPIDR_AFFLVL1 34 #define MARVELL_PWR_LVL2 MPIDR_AFFLVL2 35 36 /* 37 * Macros for local power states in Marvell platforms encoded by 38 * State-ID field within the power-state parameter. 39 */ 40 /* Local power state for power domains in Run state. */ 41 #define MARVELL_LOCAL_STATE_RUN 0 42 /* Local power state for retention. Valid only for CPU power domains */ 43 #define MARVELL_LOCAL_STATE_RET 1 44 /* 45 * Local power state for OFF/power-down. Valid for CPU 46 * and cluster power domains 47 */ 48 #define MARVELL_LOCAL_STATE_OFF 2 49 50 /* The first 4KB of Trusted SRAM are used as shared memory */ 51 #define MARVELL_TRUSTED_SRAM_BASE PLAT_MARVELL_ATF_BASE 52 #define MARVELL_SHARED_RAM_BASE MARVELL_TRUSTED_SRAM_BASE 53 #define MARVELL_SHARED_RAM_SIZE 0x00001000 /* 4 KB */ 54 55 /* The remaining Trusted SRAM is used to load the BL images */ 56 #define MARVELL_BL_RAM_BASE (MARVELL_SHARED_RAM_BASE + \ 57 MARVELL_SHARED_RAM_SIZE) 58 #define MARVELL_BL_RAM_SIZE (PLAT_MARVELL_TRUSTED_SRAM_SIZE - \ 59 MARVELL_SHARED_RAM_SIZE) 60 /* Non-shared DRAM */ 61 #define MARVELL_DRAM_BASE ULL(0x0) 62 #define MARVELL_DRAM_SIZE ULL(0x80000000) 63 #define MARVELL_DRAM_END (MARVELL_DRAM_BASE + \ 64 MARVELL_DRAM_SIZE - 1) 65 66 #define MARVELL_IRQ_PIC0 28 67 #define MARVELL_IRQ_SEC_PHY_TIMER 29 68 69 #define MARVELL_IRQ_SEC_SGI_0 8 70 #define MARVELL_IRQ_SEC_SGI_1 9 71 #define MARVELL_IRQ_SEC_SGI_2 10 72 #define MARVELL_IRQ_SEC_SGI_3 11 73 #define MARVELL_IRQ_SEC_SGI_4 12 74 #define MARVELL_IRQ_SEC_SGI_5 13 75 #define MARVELL_IRQ_SEC_SGI_6 14 76 #define MARVELL_IRQ_SEC_SGI_7 15 77 78 #define MARVELL_MAP_SHARED_RAM MAP_REGION_FLAT( \ 79 MARVELL_SHARED_RAM_BASE,\ 80 MARVELL_SHARED_RAM_SIZE,\ 81 MT_MEMORY | MT_RW | MT_SECURE) 82 83 #define MARVELL_MAP_DRAM MAP_REGION_FLAT( \ 84 MARVELL_DRAM_BASE, \ 85 MARVELL_DRAM_SIZE, \ 86 MT_MEMORY | MT_RW | MT_NS) 87 88 89 /* 90 * The number of regions like RO(code), coherent and data required by 91 * different BL stages which need to be mapped in the MMU. 92 */ 93 #if USE_COHERENT_MEM 94 #define MARVELL_BL_REGIONS 3 95 #else 96 #define MARVELL_BL_REGIONS 2 97 #endif 98 99 #define MAX_MMAP_REGIONS (PLAT_MARVELL_MMAP_ENTRIES + \ 100 MARVELL_BL_REGIONS) 101 102 #define MARVELL_CONSOLE_BAUDRATE 115200 103 104 /****************************************************************************** 105 * Required platform porting definitions common to all MARVELL std. platforms 106 *****************************************************************************/ 107 108 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 109 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 110 111 /* 112 * This macro defines the deepest retention state possible. A higher state 113 * id will represent an invalid or a power down state. 114 */ 115 #define PLAT_MAX_RET_STATE MARVELL_LOCAL_STATE_RET 116 117 /* 118 * This macro defines the deepest power down states possible. Any state ID 119 * higher than this is invalid. 120 */ 121 #define PLAT_MAX_OFF_STATE MARVELL_LOCAL_STATE_OFF 122 123 124 #define PLATFORM_CORE_COUNT PLAT_MARVELL_CORE_COUNT 125 #define PLAT_NUM_PWR_DOMAINS (PLAT_MARVELL_CLUSTER_COUNT + \ 126 PLATFORM_CORE_COUNT) 127 128 /* 129 * Some data must be aligned on the biggest cache line size in the platform. 130 * This is known only to the platform as it might have a combination of 131 * integrated and external caches. 132 */ 133 #define CACHE_WRITEBACK_GRANULE (1 << MARVELL_CACHE_WRITEBACK_SHIFT) 134 135 136 /******************************************************************************* 137 * BL1 specific defines. 138 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of 139 * addresses. 140 ******************************************************************************/ 141 #define BL1_RO_BASE PLAT_MARVELL_TRUSTED_ROM_BASE 142 #define BL1_RO_LIMIT (PLAT_MARVELL_TRUSTED_ROM_BASE \ 143 + PLAT_MARVELL_TRUSTED_ROM_SIZE) 144 /* 145 * Put BL1 RW at the top of the Trusted SRAM. 146 */ 147 #define BL1_RW_BASE (MARVELL_BL_RAM_BASE + \ 148 MARVELL_BL_RAM_SIZE - \ 149 PLAT_MARVELL_MAX_BL1_RW_SIZE) 150 #define BL1_RW_LIMIT (MARVELL_BL_RAM_BASE + MARVELL_BL_RAM_SIZE) 151 152 /******************************************************************************* 153 * BLE specific defines. 154 ******************************************************************************/ 155 #define BLE_BASE PLAT_MARVELL_SRAM_BASE 156 #define BLE_LIMIT PLAT_MARVELL_SRAM_END 157 158 /******************************************************************************* 159 * BL2 specific defines. 160 ******************************************************************************/ 161 /* 162 * Put BL2 just below BL31. 163 */ 164 #define BL2_BASE (BL31_BASE - PLAT_MARVELL_MAX_BL2_SIZE) 165 #define BL2_LIMIT BL31_BASE 166 167 /******************************************************************************* 168 * BL31 specific defines. 169 ******************************************************************************/ 170 /* 171 * Put BL31 at the top of the Trusted SRAM. 172 */ 173 #define BL31_BASE (MARVELL_BL_RAM_BASE + \ 174 MARVELL_BL_RAM_SIZE - \ 175 PLAT_MARVEL_MAX_BL31_SIZE) 176 #define BL31_PROGBITS_LIMIT BL1_RW_BASE 177 #define BL31_LIMIT (MARVELL_BL_RAM_BASE + \ 178 MARVELL_BL_RAM_SIZE) 179 180 181 #endif /* MARVELL_DEF_H */ 182