1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Common internal memory map for some Freescale SoCs 4 * 5 * Copyright 2014 Freescale Semiconductor, Inc. 6 */ 7 8 #ifndef __FSL_SEC_H 9 #define __FSL_SEC_H 10 11 #include <common.h> 12 #include <asm/io.h> 13 14 #ifdef CONFIG_SYS_FSL_SEC_LE 15 #define sec_in32(a) in_le32(a) 16 #define sec_out32(a, v) out_le32(a, v) 17 #define sec_in16(a) in_le16(a) 18 #define sec_clrbits32 clrbits_le32 19 #define sec_setbits32 setbits_le32 20 #elif defined(CONFIG_SYS_FSL_SEC_BE) 21 #define sec_in32(a) in_be32(a) 22 #define sec_out32(a, v) out_be32(a, v) 23 #define sec_in16(a) in_be16(a) 24 #define sec_clrbits32 clrbits_be32 25 #define sec_setbits32 setbits_be32 26 #elif defined(CONFIG_SYS_FSL_HAS_SEC) 27 #error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined 28 #endif 29 30 /* Security Engine Block (MS = Most Sig., LS = Least Sig.) */ 31 #if CONFIG_SYS_FSL_SEC_COMPAT >= 4 32 /* RNG4 TRNG test registers */ 33 struct rng4tst { 34 #define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */ 35 #define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC 0 /* use von Neumann data in 36 both entropy shifter and 37 statistical checker */ 38 #define RTMCTL_SAMP_MODE_RAW_ES_SC 1 /* use raw data in both 39 entropy shifter and 40 statistical checker */ 41 #define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_RAW_SC 2 /* use von Neumann data in 42 entropy shifter, raw data 43 in statistical checker */ 44 #define RTMCTL_SAMP_MODE_INVALID 3 /* invalid combination */ 45 u32 rtmctl; /* misc. control register */ 46 u32 rtscmisc; /* statistical check misc. register */ 47 u32 rtpkrrng; /* poker range register */ 48 #define RTSDCTL_ENT_DLY_MIN 3200 49 #define RTSDCTL_ENT_DLY_MAX 12800 50 union { 51 u32 rtpkrmax; /* PRGM=1: poker max. limit register */ 52 u32 rtpkrsq; /* PRGM=0: poker square calc. result register */ 53 }; 54 #define RTSDCTL_ENT_DLY_SHIFT 16 55 #define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT) 56 u32 rtsdctl; /* seed control register */ 57 union { 58 u32 rtsblim; /* PRGM=1: sparse bit limit register */ 59 u32 rttotsam; /* PRGM=0: total samples register */ 60 }; 61 u32 rtfreqmin; /* frequency count min. limit register */ 62 #define RTFRQMAX_DISABLE (1 << 20) 63 union { 64 u32 rtfreqmax; /* PRGM=1: freq. count max. limit register */ 65 u32 rtfreqcnt; /* PRGM=0: freq. count register */ 66 }; 67 u32 rsvd1[40]; 68 #define RNG_STATE0_HANDLE_INSTANTIATED 0x00000001 69 #define RNG_STATE1_HANDLE_INSTANTIATED 0x00000002 70 #define RNG_STATE_HANDLE_MASK \ 71 (RNG_STATE0_HANDLE_INSTANTIATED | RNG_STATE1_HANDLE_INSTANTIATED) 72 u32 rdsta; /*RNG DRNG Status Register*/ 73 u32 rsvd2[15]; 74 }; 75 76 typedef struct ccsr_sec { 77 u32 res0; 78 u32 mcfgr; /* Master CFG Register */ 79 u8 res1[0x4]; 80 u32 scfgr; 81 struct { 82 u32 ms; /* Job Ring LIODN Register, MS */ 83 u32 ls; /* Job Ring LIODN Register, LS */ 84 } jrliodnr[4]; 85 u8 res2[0x2c]; 86 u32 jrstartr; /* Job Ring Start Register */ 87 struct { 88 u32 ms; /* RTIC LIODN Register, MS */ 89 u32 ls; /* RTIC LIODN Register, LS */ 90 } rticliodnr[4]; 91 u8 res3[0x1c]; 92 u32 decorr; /* DECO Request Register */ 93 struct { 94 u32 ms; /* DECO LIODN Register, MS */ 95 u32 ls; /* DECO LIODN Register, LS */ 96 } decoliodnr[16]; 97 u32 dar; /* DECO Avail Register */ 98 u32 drr; /* DECO Reset Register */ 99 u8 res5[0x4d8]; 100 struct rng4tst rng; /* RNG Registers */ 101 u8 res6[0x8a0]; 102 u32 crnr_ms; /* CHA Revision Number Register, MS */ 103 u32 crnr_ls; /* CHA Revision Number Register, LS */ 104 u32 ctpr_ms; /* Compile Time Parameters Register, MS */ 105 u32 ctpr_ls; /* Compile Time Parameters Register, LS */ 106 u8 res7[0x10]; 107 u32 far_ms; /* Fault Address Register, MS */ 108 u32 far_ls; /* Fault Address Register, LS */ 109 u32 falr; /* Fault Address LIODN Register */ 110 u32 fadr; /* Fault Address Detail Register */ 111 u8 res8[0x4]; 112 u32 csta; /* CAAM Status Register */ 113 u32 smpart; /* Secure Memory Partition Parameters */ 114 u32 smvid; /* Secure Memory Version ID */ 115 u32 rvid; /* Run Time Integrity Checking Version ID Reg.*/ 116 u32 ccbvid; /* CHA Cluster Block Version ID Register */ 117 u32 chavid_ms; /* CHA Version ID Register, MS */ 118 u32 chavid_ls; /* CHA Version ID Register, LS */ 119 u32 chanum_ms; /* CHA Number Register, MS */ 120 u32 chanum_ls; /* CHA Number Register, LS */ 121 u32 secvid_ms; /* SEC Version ID Register, MS */ 122 u32 secvid_ls; /* SEC Version ID Register, LS */ 123 #if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) 124 u8 res9[0x6f020]; 125 #else 126 u8 res9[0x6020]; 127 #endif 128 u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS */ 129 u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */ 130 #if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) 131 u8 res10[0x8ffd8]; 132 #else 133 u8 res10[0x8fd8]; 134 #endif 135 } ccsr_sec_t; 136 137 #define SEC_CTPR_MS_AXI_LIODN 0x08000000 138 #define SEC_CTPR_MS_QI 0x02000000 139 #define SEC_CTPR_MS_VIRT_EN_INCL 0x00000001 140 #define SEC_CTPR_MS_VIRT_EN_POR 0x00000002 141 #define SEC_RVID_MA 0x0f000000 142 #define SEC_CHANUM_MS_JRNUM_MASK 0xf0000000 143 #define SEC_CHANUM_MS_JRNUM_SHIFT 28 144 #define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000 145 #define SEC_CHANUM_MS_DECONUM_SHIFT 24 146 #define SEC_SECVID_MS_IPID_MASK 0xffff0000 147 #define SEC_SECVID_MS_IPID_SHIFT 16 148 #define SEC_SECVID_MS_MAJ_REV_MASK 0x0000ff00 149 #define SEC_SECVID_MS_MAJ_REV_SHIFT 8 150 #define SEC_CCBVID_ERA_MASK 0xff000000 151 #define SEC_CCBVID_ERA_SHIFT 24 152 #define SEC_SCFGR_RDBENABLE 0x00000400 153 #define SEC_SCFGR_VIRT_EN 0x00008000 154 #define SEC_CHAVID_LS_RNG_SHIFT 16 155 #define SEC_CHAVID_RNG_LS_MASK 0x000f0000 156 157 #define CONFIG_JRSTARTR_JR0 0x00000001 158 159 struct jr_regs { 160 #if defined(CONFIG_SYS_FSL_SEC_LE) && \ 161 !(defined(CONFIG_MX6) || defined(CONFIG_MX7)) 162 u32 irba_l; 163 u32 irba_h; 164 #else 165 u32 irba_h; 166 u32 irba_l; 167 #endif 168 u32 rsvd1; 169 u32 irs; 170 u32 rsvd2; 171 u32 irsa; 172 u32 rsvd3; 173 u32 irja; 174 #if defined(CONFIG_SYS_FSL_SEC_LE) && \ 175 !(defined(CONFIG_MX6) || defined(CONFIG_MX7)) 176 u32 orba_l; 177 u32 orba_h; 178 #else 179 u32 orba_h; 180 u32 orba_l; 181 #endif 182 u32 rsvd4; 183 u32 ors; 184 u32 rsvd5; 185 u32 orjr; 186 u32 rsvd6; 187 u32 orsf; 188 u32 rsvd7; 189 u32 jrsta; 190 u32 rsvd8; 191 u32 jrint; 192 u32 jrcfg0; 193 u32 jrcfg1; 194 u32 rsvd9; 195 u32 irri; 196 u32 rsvd10; 197 u32 orwi; 198 u32 rsvd11; 199 u32 jrcr; 200 }; 201 202 /* 203 * Scatter Gather Entry - Specifies the the Scatter Gather Format 204 * related information 205 */ 206 struct sg_entry { 207 #if defined(CONFIG_SYS_FSL_SEC_LE) && \ 208 !(defined(CONFIG_MX6) || defined(CONFIG_MX7)) 209 uint32_t addr_lo; /* Memory Address - lo */ 210 uint32_t addr_hi; /* Memory Address of start of buffer - hi */ 211 #else 212 uint32_t addr_hi; /* Memory Address of start of buffer - hi */ 213 uint32_t addr_lo; /* Memory Address - lo */ 214 #endif 215 216 uint32_t len_flag; /* Length of the data in the frame */ 217 #define SG_ENTRY_LENGTH_MASK 0x3FFFFFFF 218 #define SG_ENTRY_EXTENSION_BIT 0x80000000 219 #define SG_ENTRY_FINAL_BIT 0x40000000 220 uint32_t bpid_offset; 221 #define SG_ENTRY_BPID_MASK 0x00FF0000 222 #define SG_ENTRY_BPID_SHIFT 16 223 #define SG_ENTRY_OFFSET_MASK 0x00001FFF 224 #define SG_ENTRY_OFFSET_SHIFT 0 225 }; 226 227 #define BLOB_SIZE(x) ((x) + 32 + 16) /* Blob buffer size */ 228 229 #if defined(CONFIG_MX6) || defined(CONFIG_MX7) 230 /* Job Ring Base Address */ 231 #define JR_BASE_ADDR(x) (CONFIG_SYS_FSL_SEC_ADDR + 0x1000 * (x + 1)) 232 /* Secure Memory Offset varies accross versions */ 233 #define SM_V1_OFFSET 0x0f4 234 #define SM_V2_OFFSET 0xa00 235 /*Secure Memory Versioning */ 236 #define SMVID_V2 0x20105 237 #define SM_VERSION(x) (x < SMVID_V2 ? 1 : 2) 238 #define SM_OFFSET(x) (x == 1 ? SM_V1_OFFSET : SM_V2_OFFSET) 239 /* CAAM Job Ring 0 Registers */ 240 /* Secure Memory Partition Owner register */ 241 #define SMCSJR_PO (3 << 6) 242 /* JR Allocation Error */ 243 #define SMCSJR_AERR (3 << 12) 244 /* Secure memory partition 0 page 0 owner register */ 245 #define CAAM_SMPO_0 (CONFIG_SYS_FSL_SEC_ADDR + 0x1FBC) 246 /* Secure memory command register */ 247 #define CAAM_SMCJR(v, jr) (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_CMD(v)) 248 /* Secure memory command status register */ 249 #define CAAM_SMCSJR(v, jr) (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_STATUS(v)) 250 /* Secure memory access permissions register */ 251 #define CAAM_SMAPJR(v, jr, y) \ 252 (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_PERM(v) + y * 16) 253 /* Secure memory access group 2 register */ 254 #define CAAM_SMAG2JR(v, jr, y) \ 255 (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_GROUP2(v) + y * 16) 256 /* Secure memory access group 1 register */ 257 #define CAAM_SMAG1JR(v, jr, y) \ 258 (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_GROUP1(v) + y * 16) 259 260 /* Commands and macros for secure memory */ 261 #define SM_CMD(v) (v == 1 ? 0x0 : 0x1E4) 262 #define SM_STATUS(v) (v == 1 ? 0x8 : 0x1EC) 263 #define SM_PERM(v) (v == 1 ? 0x10 : 0x4) 264 #define SM_GROUP2(v) (v == 1 ? 0x14 : 0x8) 265 #define SM_GROUP1(v) (v == 1 ? 0x18 : 0xC) 266 #define CMD_PAGE_ALLOC 0x1 267 #define CMD_PAGE_DEALLOC 0x2 268 #define CMD_PART_DEALLOC 0x3 269 #define CMD_INQUIRY 0x5 270 #define CMD_COMPLETE (3 << 14) 271 #define PAGE_AVAILABLE 0 272 #define PAGE_OWNED (3 << 6) 273 #define PAGE(x) (x << 16) 274 #define PARTITION(x) (x << 8) 275 #define PARTITION_OWNER(x) (0x3 << (x*2)) 276 277 /* Address of secure 4kbyte pages */ 278 #define SEC_MEM_PAGE0 CAAM_ARB_BASE_ADDR 279 #define SEC_MEM_PAGE1 (CAAM_ARB_BASE_ADDR + 0x1000) 280 #define SEC_MEM_PAGE2 (CAAM_ARB_BASE_ADDR + 0x2000) 281 #define SEC_MEM_PAGE3 (CAAM_ARB_BASE_ADDR + 0x3000) 282 283 #define JR_MID 2 /* Matches ROM configuration */ 284 #define KS_G1 (1 << JR_MID) /* CAAM only */ 285 #define PERM 0x0000B008 /* Clear on release, lock SMAP 286 * lock SMAG group 1 Blob */ 287 288 /* HAB WRAPPED KEY header */ 289 #define WRP_HDR_SIZE 0x08 290 #define HDR_TAG 0x81 291 #define HDR_PAR 0x41 292 /* HAB WRAPPED KEY Data */ 293 #define HAB_MOD 0x66 294 #define HAB_ALG 0x55 295 #define HAB_FLG 0x00 296 297 /* Partition and Page IDs */ 298 #define PARTITION_1 1 299 #define PAGE_1 1 300 301 #define ERROR_IN_PAGE_ALLOC 1 302 #define ECONSTRJDESC -1 303 304 #endif 305 306 /* blob_dek: 307 * Encapsulates the src in a secure blob and stores it dst 308 * @src: reference to the plaintext 309 * @dst: reference to the output adrress 310 * @len: size in bytes of src 311 * @return: 0 on success, error otherwise 312 */ 313 int blob_dek(const u8 *src, u8 *dst, u8 len); 314 315 #if defined(CONFIG_ARCH_C29X) 316 int sec_init_idx(uint8_t); 317 #endif 318 int sec_init(void); 319 #endif 320 321 #endif /* __FSL_SEC_H */ 322