1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de> 4 */ 5 6 #ifndef _CONFIG_THEADORABLE_H 7 #define _CONFIG_THEADORABLE_H 8 9 /* 10 * High Level Configuration Options (easy to change) 11 */ 12 13 /* 14 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed 15 * for DDR ECC byte filling in the SPL before loading the main 16 * U-Boot into it. 17 */ 18 #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ 19 20 /* 21 * Commands configuration 22 */ 23 24 /* 25 * The debugging version enables USB support via defconfig. 26 * This version should also enable all other non-production 27 * interfaces / features. 28 */ 29 30 /* I2C */ 31 #define CONFIG_SYS_I2C 32 #define CONFIG_SYS_I2C_MVTWSI 33 #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE 34 #define CONFIG_I2C_MVTWSI_BASE1 MVEBU_TWSI1_BASE 35 #define CONFIG_SYS_I2C_SLAVE 0x0 36 #define CONFIG_SYS_I2C_SPEED 100000 37 38 /* USB/EHCI configuration */ 39 #define CONFIG_EHCI_IS_TDI 40 #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 41 42 /* Environment in SPI NOR flash */ 43 #define CONFIG_ENV_OVERWRITE 44 45 #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ 46 47 /* Keep device tree and initrd in lower memory so the kernel can access them */ 48 #define CONFIG_EXTRA_ENV_SETTINGS \ 49 "fdt_high=0x10000000\0" \ 50 "initrd_high=0x10000000\0" 51 52 /* SATA support */ 53 #define CONFIG_SYS_SATA_MAX_DEVICE 1 54 #define CONFIG_LBA48 55 56 /* Enable LCD and reserve 512KB from top of memory*/ 57 #define CONFIG_SYS_MEM_TOP_HIDE 0x80000 58 59 #define CONFIG_BMP_16BPP 60 #define CONFIG_BMP_24BPP 61 #define CONFIG_BMP_32BPP 62 63 /* FPGA programming support */ 64 #define CONFIG_FPGA_STRATIX_V 65 66 /* 67 * Bootcounter 68 */ 69 /* Max size of RAM minus BOOTCOUNT_ADDR is the bootcounter address */ 70 #define BOOTCOUNT_ADDR 0x1000 71 72 /* 73 * mv-common.h should be defined after CMD configs since it used them 74 * to enable certain macros 75 */ 76 #include "mv-common.h" 77 78 /* 79 * Memory layout while starting into the bin_hdr via the 80 * BootROM: 81 * 82 * 0x4000.4000 - 0x4003.4000 headers space (192KiB) 83 * 0x4000.4030 bin_hdr start address 84 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) 85 * 0x4007.fffc BootROM stack top 86 * 87 * The address space between 0x4007.fffc and 0x400f.fff is not locked in 88 * L2 cache thus cannot be used. 89 */ 90 91 /* SPL */ 92 /* Defines for SPL */ 93 #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) 94 95 #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) 96 #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) 97 98 #ifdef CONFIG_SPL_BUILD 99 #define CONFIG_SYS_MALLOC_SIMPLE 100 #endif 101 102 #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) 103 #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) 104 105 /* SPL related SPI defines */ 106 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS 107 108 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ 109 #define CONFIG_DDR_FIXED_SIZE (2 << 20) /* 2GiB */ 110 111 #endif /* _CONFIG_THEADORABLE_H */ 112