1# 2# Multifunction miscellaneous devices 3# 4 5menu "Multifunction device drivers" 6 7config MISC 8 bool "Enable Driver Model for Misc drivers" 9 depends on DM 10 help 11 Enable driver model for miscellaneous devices. This class is 12 used only for those do not fit other more general classes. A 13 set of generic read, write and ioctl methods may be used to 14 access the device. 15 16config SPL_MISC 17 bool "Enable Driver Model for Misc drivers in SPL" 18 depends on SPL_DM 19 help 20 Enable driver model for miscellaneous devices. This class is 21 used only for those do not fit other more general classes. A 22 set of generic read, write and ioctl methods may be used to 23 access the device. 24 25config TPL_MISC 26 bool "Enable Driver Model for Misc drivers in TPL" 27 depends on TPL_DM 28 help 29 Enable driver model for miscellaneous devices. This class is 30 used only for those do not fit other more general classes. A 31 set of generic read, write and ioctl methods may be used to 32 access the device. 33 34config ALTERA_SYSID 35 bool "Altera Sysid support" 36 depends on MISC 37 help 38 Select this to enable a sysid for Altera devices. Please find 39 details on the "Embedded Peripherals IP User Guide" of Altera. 40 41config ATSHA204A 42 bool "Support for Atmel ATSHA204A module" 43 depends on MISC 44 help 45 Enable support for I2C connected Atmel's ATSHA204A 46 CryptoAuthentication module found for example on the Turris Omnia 47 board. 48 49config ROCKCHIP_EFUSE 50 bool "Rockchip e-fuse support" 51 depends on MISC 52 help 53 Enable (read-only) access for the e-fuse block found in Rockchip 54 SoCs: accesses can either be made using byte addressing and a length 55 or through child-nodes that are generated based on the e-fuse map 56 retrieved from the DTS. 57 58 This driver currently supports the RK3399 only, but can easily be 59 extended (by porting the read function from the Linux kernel sources) 60 to support other recent Rockchip devices. 61 62config ROCKCHIP_OTP 63 bool "Rockchip OTP Support" 64 depends on MISC 65 help 66 Enable (read-only) access for the one-time-programmable memory block 67 found in Rockchip SoCs: accesses can either be made using byte 68 addressing and a length or through child-nodes that are generated 69 based on the e-fuse map retrieved from the DTS. 70 71config VEXPRESS_CONFIG 72 bool "Enable support for Arm Versatile Express config bus" 73 depends on MISC 74 help 75 If you say Y here, you will get support for accessing the 76 configuration bus on the Arm Versatile Express boards via 77 a sysreg driver. 78 79config CMD_CROS_EC 80 bool "Enable crosec command" 81 depends on CROS_EC 82 help 83 Enable command-line access to the Chrome OS EC (Embedded 84 Controller). This provides the 'crosec' command which has 85 a number of sub-commands for performing EC tasks such as 86 updating its flash, accessing a small saved context area 87 and talking to the I2C bus behind the EC (if there is one). 88 89config CROS_EC 90 bool "Enable Chrome OS EC" 91 help 92 Enable access to the Chrome OS EC. This is a separate 93 microcontroller typically available on a SPI bus on Chromebooks. It 94 provides access to the keyboard, some internal storage and may 95 control access to the battery and main PMIC depending on the 96 device. You can use the 'crosec' command to access it. 97 98config SPL_CROS_EC 99 bool "Enable Chrome OS EC in SPL" 100 depends on SPL 101 help 102 Enable access to the Chrome OS EC in SPL. This is a separate 103 microcontroller typically available on a SPI bus on Chromebooks. It 104 provides access to the keyboard, some internal storage and may 105 control access to the battery and main PMIC depending on the 106 device. You can use the 'crosec' command to access it. 107 108config TPL_CROS_EC 109 bool "Enable Chrome OS EC in TPL" 110 depends on TPL 111 help 112 Enable access to the Chrome OS EC in TPL. This is a separate 113 microcontroller typically available on a SPI bus on Chromebooks. It 114 provides access to the keyboard, some internal storage and may 115 control access to the battery and main PMIC depending on the 116 device. You can use the 'crosec' command to access it. 117 118config CROS_EC_I2C 119 bool "Enable Chrome OS EC I2C driver" 120 depends on CROS_EC 121 help 122 Enable I2C access to the Chrome OS EC. This is used on older 123 ARM Chromebooks such as snow and spring before the standard bus 124 changed to SPI. The EC will accept commands across the I2C using 125 a special message protocol, and provide responses. 126 127config CROS_EC_LPC 128 bool "Enable Chrome OS EC LPC driver" 129 depends on CROS_EC 130 help 131 Enable I2C access to the Chrome OS EC. This is used on x86 132 Chromebooks such as link and falco. The keyboard is provided 133 through a legacy port interface, so on x86 machines the main 134 function of the EC is power and thermal management. 135 136config SPL_CROS_EC_LPC 137 bool "Enable Chrome OS EC LPC driver in SPL" 138 depends on CROS_EC 139 help 140 Enable I2C access to the Chrome OS EC. This is used on x86 141 Chromebooks such as link and falco. The keyboard is provided 142 through a legacy port interface, so on x86 machines the main 143 function of the EC is power and thermal management. 144 145config TPL_CROS_EC_LPC 146 bool "Enable Chrome OS EC LPC driver in TPL" 147 depends on CROS_EC 148 help 149 Enable I2C access to the Chrome OS EC. This is used on x86 150 Chromebooks such as link and falco. The keyboard is provided 151 through a legacy port interface, so on x86 machines the main 152 function of the EC is power and thermal management. 153 154config CROS_EC_SANDBOX 155 bool "Enable Chrome OS EC sandbox driver" 156 depends on CROS_EC && SANDBOX 157 help 158 Enable a sandbox emulation of the Chrome OS EC. This supports 159 keyboard (use the -l flag to enable the LCD), verified boot context, 160 EC flash read/write/erase support and a few other things. It is 161 enough to perform a Chrome OS verified boot on sandbox. 162 163config SPL_CROS_EC_SANDBOX 164 bool "Enable Chrome OS EC sandbox driver in SPL" 165 depends on SPL_CROS_EC && SANDBOX 166 help 167 Enable a sandbox emulation of the Chrome OS EC in SPL. This supports 168 keyboard (use the -l flag to enable the LCD), verified boot context, 169 EC flash read/write/erase support and a few other things. It is 170 enough to perform a Chrome OS verified boot on sandbox. 171 172config TPL_CROS_EC_SANDBOX 173 bool "Enable Chrome OS EC sandbox driver in TPL" 174 depends on TPL_CROS_EC && SANDBOX 175 help 176 Enable a sandbox emulation of the Chrome OS EC in TPL. This supports 177 keyboard (use the -l flag to enable the LCD), verified boot context, 178 EC flash read/write/erase support and a few other things. It is 179 enough to perform a Chrome OS verified boot on sandbox. 180 181config CROS_EC_SPI 182 bool "Enable Chrome OS EC SPI driver" 183 depends on CROS_EC 184 help 185 Enable SPI access to the Chrome OS EC. This is used on newer 186 ARM Chromebooks such as pit, pi and nyan-big. The SPI interface 187 provides a faster and more robust interface than I2C but the bugs 188 are less interesting. 189 190config DS4510 191 bool "Enable support for DS4510 CPU supervisor" 192 help 193 Enable support for the Maxim DS4510 CPU supervisor. It has an 194 integrated 64-byte EEPROM, four programmable non-volatile I/O pins 195 and a configurable timer for the supervisor function. The device is 196 connected over I2C. 197 198config FSL_SEC_MON 199 bool "Enable FSL SEC_MON Driver" 200 help 201 Freescale Security Monitor block is responsible for monitoring 202 system states. 203 Security Monitor can be transitioned on any security failures, 204 like software violations or hardware security violations. 205 206config JZ4780_EFUSE 207 bool "Ingenic JZ4780 eFUSE support" 208 depends on ARCH_JZ47XX 209 help 210 This selects support for the eFUSE on Ingenic JZ4780 SoCs. 211 212config MXC_OCOTP 213 bool "Enable MXC OCOTP Driver" 214 depends on ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610 215 default y 216 help 217 If you say Y here, you will get support for the One Time 218 Programmable memory pages that are stored on the some 219 Freescale i.MX processors. 220 221config NUVOTON_NCT6102D 222 bool "Enable Nuvoton NCT6102D Super I/O driver" 223 help 224 If you say Y here, you will get support for the Nuvoton 225 NCT6102D Super I/O driver. This can be used to enable or 226 disable the legacy UART, the watchdog or other devices 227 in the Nuvoton Super IO chips on X86 platforms. 228 229config PWRSEQ 230 bool "Enable power-sequencing drivers" 231 depends on DM 232 help 233 Power-sequencing drivers provide support for controlling power for 234 devices. They are typically referenced by a phandle from another 235 device. When the device is started up, its power sequence can be 236 initiated. 237 238config SPL_PWRSEQ 239 bool "Enable power-sequencing drivers for SPL" 240 depends on PWRSEQ 241 help 242 Power-sequencing drivers provide support for controlling power for 243 devices. They are typically referenced by a phandle from another 244 device. When the device is started up, its power sequence can be 245 initiated. 246 247config PCA9551_LED 248 bool "Enable PCA9551 LED driver" 249 help 250 Enable driver for PCA9551 LED controller. This controller 251 is connected via I2C. So I2C needs to be enabled. 252 253config PCA9551_I2C_ADDR 254 hex "I2C address of PCA9551 LED controller" 255 depends on PCA9551_LED 256 default 0x60 257 help 258 The I2C address of the PCA9551 LED controller. 259 260config STM32MP_FUSE 261 bool "Enable STM32MP fuse wrapper providing the fuse API" 262 depends on ARCH_STM32MP && MISC 263 default y if CMD_FUSE 264 help 265 If you say Y here, you will get support for the fuse API (OTP) 266 for STM32MP architecture. 267 This API is needed for CMD_FUSE. 268 269config STM32_RCC 270 bool "Enable RCC driver for the STM32 SoC's family" 271 depends on (STM32 || ARCH_STM32MP) && MISC 272 help 273 Enable the STM32 RCC driver. The RCC block (Reset and Clock Control 274 block) is responsible of the management of the clock and reset 275 generation. 276 This driver is similar to an MFD driver in the Linux kernel. 277 278config TEGRA_CAR 279 bool "Enable support for the Tegra CAR driver" 280 depends on TEGRA_NO_BPMP 281 help 282 The Tegra CAR (Clock and Reset Controller) is a HW module that 283 controls almost all clocks and resets in a Tegra SoC. 284 285config TEGRA186_BPMP 286 bool "Enable support for the Tegra186 BPMP driver" 287 depends on TEGRA186 288 help 289 The Tegra BPMP (Boot and Power Management Processor) is a separate 290 auxiliary CPU embedded into Tegra to perform power management work, 291 and controls related features such as clocks, resets, power domains, 292 PMIC I2C bus, etc. This driver provides the core low-level 293 communication path by which feature-specific drivers (such as clock) 294 can make requests to the BPMP. This driver is similar to an MFD 295 driver in the Linux kernel. 296 297config TWL4030_LED 298 bool "Enable TWL4030 LED controller" 299 help 300 Enable this to add support for the TWL4030 LED controller. 301 302config WINBOND_W83627 303 bool "Enable Winbond Super I/O driver" 304 help 305 If you say Y here, you will get support for the Winbond 306 W83627 Super I/O driver. This can be used to enable the 307 legacy UART or other devices in the Winbond Super IO chips 308 on X86 platforms. 309 310config QFW 311 bool 312 help 313 Hidden option to enable QEMU fw_cfg interface. This will be selected by 314 either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE. 315 316config I2C_EEPROM 317 bool "Enable driver for generic I2C-attached EEPROMs" 318 depends on MISC 319 help 320 Enable a generic driver for EEPROMs attached via I2C. 321 322 323config SPL_I2C_EEPROM 324 bool "Enable driver for generic I2C-attached EEPROMs for SPL" 325 depends on MISC && SPL && SPL_DM 326 help 327 This option is an SPL-variant of the I2C_EEPROM option. 328 See the help of I2C_EEPROM for details. 329 330config ZYNQ_GEM_I2C_MAC_OFFSET 331 hex "Set the I2C MAC offset" 332 default 0x0 333 depends on DM_I2C 334 help 335 Set the MAC offset for i2C. 336 337if I2C_EEPROM 338 339config SYS_I2C_EEPROM_ADDR 340 hex "Chip address of the EEPROM device" 341 default 0 342 343config SYS_I2C_EEPROM_BUS 344 int "I2C bus of the EEPROM device." 345 default 0 346 347config SYS_EEPROM_SIZE 348 int "Size in bytes of the EEPROM device" 349 default 256 350 351config SYS_EEPROM_PAGE_WRITE_BITS 352 int "Number of bits used to address bytes in a single page" 353 default 0 354 help 355 The EEPROM page size is 2^SYS_EEPROM_PAGE_WRITE_BITS. 356 A 64 byte page, for example would require six bits. 357 358config SYS_EEPROM_PAGE_WRITE_DELAY_MS 359 int "Number of milliseconds to delay between page writes" 360 default 0 361 362config SYS_I2C_EEPROM_ADDR_LEN 363 int "Length in bytes of the EEPROM memory array address" 364 default 1 365 help 366 Note: This is NOT the chip address length! 367 368config SYS_I2C_EEPROM_ADDR_OVERFLOW 369 hex "EEPROM Address Overflow" 370 default 0 371 help 372 EEPROM chips that implement "address overflow" are ones 373 like Catalyst 24WC04/08/16 which has 9/10/11 bits of 374 address and the extra bits end up in the "chip address" bit 375 slots. This makes a 24WC08 (1Kbyte) chip look like four 256 376 byte chips. 377 378endif 379 380config GDSYS_RXAUI_CTRL 381 bool "Enable gdsys RXAUI control driver" 382 depends on MISC 383 help 384 Support gdsys FPGA's RXAUI control. 385 386config GDSYS_IOEP 387 bool "Enable gdsys IOEP driver" 388 depends on MISC 389 help 390 Support gdsys FPGA's IO endpoint driver. 391 392config MPC83XX_SERDES 393 bool "Enable MPC83xx serdes driver" 394 depends on MISC 395 help 396 Support for serdes found on MPC83xx SoCs. 397 398config FS_LOADER 399 bool "Enable loader driver for file system" 400 help 401 This is file system generic loader which can be used to load 402 the file image from the storage into target such as memory. 403 404 The consumer driver would then use this loader to program whatever, 405 ie. the FPGA device. 406 407config GDSYS_SOC 408 bool "Enable gdsys SOC driver" 409 depends on MISC 410 help 411 Support for gdsys IHS SOC, a simple bus associated with each gdsys 412 IHS (Integrated Hardware Systems) FPGA, which holds all devices whose 413 register maps are contained within the FPGA's register map. 414 415config IHS_FPGA 416 bool "Enable IHS FPGA driver" 417 depends on MISC 418 help 419 Support IHS (Integrated Hardware Systems) FPGA, the main FPGAs on 420 gdsys devices, which supply the majority of the functionality offered 421 by the devices. This driver supports both CON and CPU variants of the 422 devices, depending on the device tree entry. 423 424config MICROCHIP_FLEXCOM 425 bool "Enable Microchip Flexcom driver" 426 depends on MISC 427 help 428 The Atmel Flexcom is just a wrapper which embeds a SPI controller, 429 an I2C controller and an USART. 430 Only one function can be used at a time and is chosen at boot time 431 according to the device tree. 432 433config K3_AVS0 434 depends on ARCH_K3 && SPL_DM_REGULATOR 435 bool "AVS class 0 support for K3 devices" 436 help 437 K3 devices have the optimized voltage values for the main voltage 438 domains stored in efuse within the VTM IP. This driver reads the 439 optimized voltage from the efuse, so that it can be programmed 440 to the PMIC on board. 441 442endmenu 443