1 2menuconfig MTD_RAW_NAND 3 bool "Raw NAND Device Support" 4if MTD_RAW_NAND 5 6config SYS_NAND_SELF_INIT 7 bool 8 help 9 This option, if enabled, provides more flexible and linux-like 10 NAND initialization process. 11 12config SYS_NAND_DRIVER_ECC_LAYOUT 13 bool 14 help 15 Omit standard ECC layouts to safe space. Select this if your driver 16 is known to provide its own ECC layout. 17 18config SYS_NAND_USE_FLASH_BBT 19 bool "Enable BBT (Bad Block Table) support" 20 help 21 Enable the BBT (Bad Block Table) usage. 22 23config NAND_ATMEL 24 bool "Support Atmel NAND controller" 25 imply SYS_NAND_USE_FLASH_BBT 26 help 27 Enable this driver for NAND flash platforms using an Atmel NAND 28 controller. 29 30if NAND_ATMEL 31 32config ATMEL_NAND_HWECC 33 bool "Atmel Hardware ECC" 34 default n 35 36config ATMEL_NAND_HW_PMECC 37 bool "Atmel Programmable Multibit ECC (PMECC)" 38 select ATMEL_NAND_HWECC 39 default n 40 help 41 The Programmable Multibit ECC (PMECC) controller is a programmable 42 binary BCH(Bose, Chaudhuri and Hocquenghem) encoder and decoder. 43 44config PMECC_CAP 45 int "PMECC Correctable ECC Bits" 46 depends on ATMEL_NAND_HW_PMECC 47 default 2 48 help 49 Correctable ECC bits, can be 2, 4, 8, 12, and 24. 50 51config PMECC_SECTOR_SIZE 52 int "PMECC Sector Size" 53 depends on ATMEL_NAND_HW_PMECC 54 default 512 55 help 56 Sector size, in bytes, can be 512 or 1024. 57 58config SPL_GENERATE_ATMEL_PMECC_HEADER 59 bool "Atmel PMECC Header Generation" 60 select ATMEL_NAND_HWECC 61 select ATMEL_NAND_HW_PMECC 62 default n 63 help 64 Generate Programmable Multibit ECC (PMECC) header for SPL image. 65 66endif 67 68config NAND_BRCMNAND 69 bool "Support Broadcom NAND controller" 70 depends on OF_CONTROL && DM && DM_MTD 71 help 72 Enable the driver for NAND flash on platforms using a Broadcom NAND 73 controller. 74 75config NAND_BRCMNAND_6368 76 bool "Support Broadcom NAND controller on bcm6368" 77 depends on NAND_BRCMNAND && ARCH_BMIPS 78 help 79 Enable support for broadcom nand driver on bcm6368. 80 81config NAND_BRCMNAND_6838 82 bool "Support Broadcom NAND controller on bcm6838" 83 depends on NAND_BRCMNAND && ARCH_BMIPS && SOC_BMIPS_BCM6838 84 help 85 Enable support for broadcom nand driver on bcm6838. 86 87config NAND_BRCMNAND_6858 88 bool "Support Broadcom NAND controller on bcm6858" 89 depends on NAND_BRCMNAND && ARCH_BCM6858 90 help 91 Enable support for broadcom nand driver on bcm6858. 92 93config NAND_BRCMNAND_63158 94 bool "Support Broadcom NAND controller on bcm63158" 95 depends on NAND_BRCMNAND && ARCH_BCM63158 96 help 97 Enable support for broadcom nand driver on bcm63158. 98 99config NAND_DAVINCI 100 bool "Support TI Davinci NAND controller" 101 help 102 Enable this driver for NAND flash controllers available in TI Davinci 103 and Keystone2 platforms 104 105config NAND_DENALI 106 bool 107 select SYS_NAND_SELF_INIT 108 imply CMD_NAND 109 110config NAND_DENALI_DT 111 bool "Support Denali NAND controller as a DT device" 112 select NAND_DENALI 113 depends on OF_CONTROL && DM 114 help 115 Enable the driver for NAND flash on platforms using a Denali NAND 116 controller as a DT device. 117 118config NAND_DENALI_SPARE_AREA_SKIP_BYTES 119 int "Number of bytes skipped in OOB area" 120 depends on NAND_DENALI 121 range 0 63 122 help 123 This option specifies the number of bytes to skip from the beginning 124 of OOB area before last ECC sector data starts. This is potentially 125 used to preserve the bad block marker in the OOB area. 126 127config NAND_LPC32XX_SLC 128 bool "Support LPC32XX_SLC controller" 129 help 130 Enable the LPC32XX SLC NAND controller. 131 132config NAND_OMAP_GPMC 133 bool "Support OMAP GPMC NAND controller" 134 depends on ARCH_OMAP2PLUS 135 help 136 Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms. 137 GPMC controller is used for parallel NAND flash devices, and can 138 do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8 139 and BCH16 ECC algorithms. 140 141config NAND_OMAP_GPMC_PREFETCH 142 bool "Enable GPMC Prefetch" 143 depends on NAND_OMAP_GPMC 144 default y 145 help 146 On OMAP platforms that use the GPMC controller 147 (CONFIG_NAND_OMAP_GPMC_PREFETCH), this options enables the code that 148 uses the prefetch mode to speed up read operations. 149 150config NAND_OMAP_ELM 151 bool "Enable ELM driver for OMAPxx and AMxx platforms." 152 depends on NAND_OMAP_GPMC && !OMAP34XX 153 help 154 ELM controller is used for ECC error detection (not ECC calculation) 155 of BCH4, BCH8 and BCH16 ECC algorithms. 156 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine, 157 thus such SoC platforms need to depend on software library for ECC error 158 detection. However ECC calculation on such plaforms would still be 159 done by GPMC controller. 160 161config NAND_VF610_NFC 162 bool "Support for Freescale NFC for VF610" 163 select SYS_NAND_SELF_INIT 164 select SYS_NAND_DRIVER_ECC_LAYOUT 165 imply CMD_NAND 166 help 167 Enables support for NAND Flash Controller on some Freescale 168 processors like the VF610, MCF54418 or Kinetis K70. 169 The driver supports a maximum 2k page size. The driver 170 currently does not support hardware ECC. 171 172if NAND_VF610_NFC 173 174config NAND_VF610_NFC_DT 175 bool "Support Vybrid's vf610 NAND controller as a DT device" 176 depends on OF_CONTROL && DM_MTD 177 help 178 Enable the driver for Vybrid's vf610 NAND flash on platforms 179 using device tree. 180 181choice 182 prompt "Hardware ECC strength" 183 depends on NAND_VF610_NFC 184 default SYS_NAND_VF610_NFC_45_ECC_BYTES 185 help 186 Select the ECC strength used in the hardware BCH ECC block. 187 188config SYS_NAND_VF610_NFC_45_ECC_BYTES 189 bool "24-error correction (45 ECC bytes)" 190 191config SYS_NAND_VF610_NFC_60_ECC_BYTES 192 bool "32-error correction (60 ECC bytes)" 193 194endchoice 195 196endif 197 198config NAND_PXA3XX 199 bool "Support for NAND on PXA3xx and Armada 370/XP/38x" 200 select SYS_NAND_SELF_INIT 201 imply CMD_NAND 202 help 203 This enables the driver for the NAND flash device found on 204 PXA3xx processors (NFCv1) and also on Armada 370/XP (NFCv2). 205 206config NAND_SUNXI 207 bool "Support for NAND on Allwinner SoCs" 208 default ARCH_SUNXI 209 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I 210 select SYS_NAND_SELF_INIT 211 select SYS_NAND_U_BOOT_LOCATIONS 212 select SPL_NAND_SUPPORT 213 imply CMD_NAND 214 ---help--- 215 Enable support for NAND. This option enables the standard and 216 SPL drivers. 217 The SPL driver only supports reading from the NAND using DMA 218 transfers. 219 220if NAND_SUNXI 221 222config NAND_SUNXI_SPL_ECC_STRENGTH 223 int "Allwinner NAND SPL ECC Strength" 224 default 64 225 226config NAND_SUNXI_SPL_ECC_SIZE 227 int "Allwinner NAND SPL ECC Step Size" 228 default 1024 229 230config NAND_SUNXI_SPL_USABLE_PAGE_SIZE 231 int "Allwinner NAND SPL Usable Page Size" 232 default 1024 233 234endif 235 236config NAND_ARASAN 237 bool "Configure Arasan Nand" 238 select SYS_NAND_SELF_INIT 239 imply CMD_NAND 240 help 241 This enables Nand driver support for Arasan nand flash 242 controller. This uses the hardware ECC for read and 243 write operations. 244 245config NAND_MXC 246 bool "MXC NAND support" 247 depends on CPU_ARM926EJS || CPU_ARM1136 || MX5 248 imply CMD_NAND 249 help 250 This enables the NAND driver for the NAND flash controller on the 251 i.MX27 / i.MX31 / i.MX5 rocessors. 252 253config NAND_MXS 254 bool "MXS NAND support" 255 depends on MX23 || MX28 || MX6 || MX7 256 select SYS_NAND_SELF_INIT 257 imply CMD_NAND 258 select APBH_DMA 259 select APBH_DMA_BURST if ARCH_MX6 || ARCH_MX7 260 select APBH_DMA_BURST8 if ARCH_MX6 || ARCH_MX7 261 help 262 This enables NAND driver for the NAND flash controller on the 263 MXS processors. 264 265if NAND_MXS 266 267config NAND_MXS_DT 268 bool "Support MXS NAND controller as a DT device" 269 depends on OF_CONTROL && DM_MTD 270 help 271 Enable the driver for MXS NAND flash on platforms using 272 device tree. 273 274config NAND_MXS_USE_MINIMUM_ECC 275 bool "Use minimum ECC strength supported by the controller" 276 default false 277 278endif 279 280config NAND_ZYNQ 281 bool "Support for Zynq Nand controller" 282 select SYS_NAND_SELF_INIT 283 imply CMD_NAND 284 help 285 This enables Nand driver support for Nand flash controller 286 found on Zynq SoC. 287 288config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS 289 bool "Enable use of 1st stage bootloader timing for NAND" 290 depends on NAND_ZYNQ 291 help 292 This flag prevent U-boot reconfigure NAND flash controller and reuse 293 the NAND timing from 1st stage bootloader. 294 295config NAND_STM32_FMC2 296 bool "Support for NAND controller on STM32MP SoCs" 297 depends on ARCH_STM32MP 298 select SYS_NAND_SELF_INIT 299 imply CMD_NAND 300 help 301 Enables support for NAND Flash chips on SoCs containing the FMC2 302 NAND controller. This controller is found on STM32MP SoCs. 303 The controller supports a maximum 8k page size and supports 304 a maximum 8-bit correction error per sector of 512 bytes. 305 306comment "Generic NAND options" 307 308config SYS_NAND_BLOCK_SIZE 309 hex "NAND chip eraseblock size" 310 depends on ARCH_SUNXI 311 help 312 Number of data bytes in one eraseblock for the NAND chip on the 313 board. This is the multiple of NAND_PAGE_SIZE and the number of 314 pages. 315 316config SYS_NAND_PAGE_SIZE 317 hex "NAND chip page size" 318 depends on ARCH_SUNXI 319 help 320 Number of data bytes in one page for the NAND chip on the 321 board, not including the OOB area. 322 323config SYS_NAND_OOBSIZE 324 hex "NAND chip OOB size" 325 depends on ARCH_SUNXI 326 help 327 Number of bytes in the Out-Of-Band area for the NAND chip on 328 the board. 329 330# Enhance depends when converting drivers to Kconfig which use this config 331# option (mxc_nand, ndfc, omap_gpmc). 332config SYS_NAND_BUSWIDTH_16BIT 333 bool "Use 16-bit NAND interface" 334 depends on NAND_VF610_NFC || NAND_OMAP_GPMC || NAND_MXC || ARCH_DAVINCI 335 help 336 Indicates that NAND device has 16-bit wide data-bus. In absence of this 337 config, bus-width of NAND device is assumed to be either 8-bit and later 338 determined by reading ONFI params. 339 Above config is useful when NAND device's bus-width information cannot 340 be determined from on-chip ONFI params, like in following scenarios: 341 - SPL boot does not support reading of ONFI parameters. This is done to 342 keep SPL code foot-print small. 343 - In current U-Boot flow using nand_init(), driver initialization 344 happens in board_nand_init() which is called before any device probe 345 (nand_scan_ident + nand_scan_tail), thus device's ONFI parameters are 346 not available while configuring controller. So a static CONFIG_NAND_xx 347 is needed to know the device's bus-width in advance. 348 349config SYS_NAND_MAX_CHIPS 350 int "NAND max chips" 351 default 1 352 depends on NAND_ARASAN 353 help 354 The maximum number of NAND chips per device to be supported. 355 356if SPL 357 358config SYS_NAND_U_BOOT_LOCATIONS 359 bool "Define U-boot binaries locations in NAND" 360 help 361 Enable CONFIG_SYS_NAND_U_BOOT_OFFS though Kconfig. 362 This option should not be enabled when compiling U-boot for boards 363 defining CONFIG_SYS_NAND_U_BOOT_OFFS in their include/configs/<board>.h 364 file. 365 366config SYS_NAND_U_BOOT_OFFS 367 hex "Location in NAND to read U-Boot from" 368 default 0x800000 if NAND_SUNXI 369 depends on SYS_NAND_U_BOOT_LOCATIONS 370 help 371 Set the offset from the start of the nand where u-boot should be 372 loaded from. 373 374config SYS_NAND_U_BOOT_OFFS_REDUND 375 hex "Location in NAND to read U-Boot from" 376 default SYS_NAND_U_BOOT_OFFS 377 depends on SYS_NAND_U_BOOT_LOCATIONS 378 help 379 Set the offset from the start of the nand where the redundant u-boot 380 should be loaded from. 381 382config SPL_NAND_AM33XX_BCH 383 bool "Enables SPL-NAND driver which supports ELM based" 384 depends on NAND_OMAP_GPMC && !OMAP34XX 385 default y 386 help 387 Hardware ECC correction. This is useful for platforms which have ELM 388 hardware engine and use NAND boot mode. 389 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine, 390 so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling 391 SPL-NAND driver with software ECC correction support. 392 393config SPL_NAND_DENALI 394 bool "Support Denali NAND controller for SPL" 395 help 396 This is a small implementation of the Denali NAND controller 397 for use on SPL. 398 399config SPL_NAND_SIMPLE 400 bool "Use simple SPL NAND driver" 401 depends on !SPL_NAND_AM33XX_BCH 402 help 403 Support for NAND boot using simple NAND drivers that 404 expose the cmd_ctrl() interface. 405endif 406 407endif # if NAND 408