1menu "MIPS architecture" 2 depends on MIPS 3 4config SYS_ARCH 5 default "mips" 6 7config SYS_CPU 8 default "mips32" if CPU_MIPS32 9 default "mips64" if CPU_MIPS64 10 11choice 12 prompt "Target select" 13 optional 14 15config TARGET_QEMU_MIPS 16 bool "Support qemu-mips" 17 select ROM_EXCEPTION_VECTORS 18 select SUPPORTS_BIG_ENDIAN 19 select SUPPORTS_CPU_MIPS32_R1 20 select SUPPORTS_CPU_MIPS32_R2 21 select SUPPORTS_CPU_MIPS64_R1 22 select SUPPORTS_CPU_MIPS64_R2 23 select SUPPORTS_LITTLE_ENDIAN 24 25config TARGET_MALTA 26 bool "Support malta" 27 select DM 28 select DM_SERIAL 29 select DYNAMIC_IO_PORT_BASE 30 select MIPS_CM 31 select MIPS_INSERT_BOOT_CONFIG 32 select MIPS_L1_CACHE_SHIFT_6 33 select MIPS_L2_CACHE 34 select OF_CONTROL 35 select OF_ISA_BUS 36 select ROM_EXCEPTION_VECTORS 37 select SUPPORTS_BIG_ENDIAN 38 select SUPPORTS_CPU_MIPS32_R1 39 select SUPPORTS_CPU_MIPS32_R2 40 select SUPPORTS_CPU_MIPS32_R6 41 select SUPPORTS_CPU_MIPS64_R1 42 select SUPPORTS_CPU_MIPS64_R2 43 select SUPPORTS_CPU_MIPS64_R6 44 select SUPPORTS_LITTLE_ENDIAN 45 select SWAP_IO_SPACE 46 imply CMD_DM 47 48config TARGET_VCT 49 bool "Support vct" 50 select ROM_EXCEPTION_VECTORS 51 select SUPPORTS_BIG_ENDIAN 52 select SUPPORTS_CPU_MIPS32_R1 53 select SUPPORTS_CPU_MIPS32_R2 54 select SYS_MIPS_CACHE_INIT_RAM_LOAD 55 56config ARCH_ATH79 57 bool "Support QCA/Atheros ath79" 58 select DM 59 select OF_CONTROL 60 imply CMD_DM 61 62config ARCH_MSCC 63 bool "Support MSCC VCore-III" 64 select OF_CONTROL 65 select DM 66 67config ARCH_BMIPS 68 bool "Support BMIPS SoCs" 69 select CLK 70 select CPU 71 select DM 72 select OF_CONTROL 73 select RAM 74 select SYSRESET 75 imply CMD_DM 76 77config ARCH_MTMIPS 78 bool "Support MediaTek MIPS platforms" 79 select CLK 80 imply CMD_DM 81 select DISPLAY_CPUINFO 82 select DM 83 imply DM_ETH 84 imply DM_GPIO 85 select DM_RESET 86 select DM_SERIAL 87 select PINCTRL 88 select PINMUX 89 select PINCONF 90 select RESET_MTMIPS 91 imply DM_SPI 92 imply DM_SPI_FLASH 93 select LAST_STAGE_INIT 94 select MIPS_TUNE_24KC 95 select OF_CONTROL 96 select ROM_EXCEPTION_VECTORS 97 select SUPPORTS_CPU_MIPS32_R1 98 select SUPPORTS_CPU_MIPS32_R2 99 select SUPPORTS_LITTLE_ENDIAN 100 select SYSRESET 101 102config ARCH_JZ47XX 103 bool "Support Ingenic JZ47xx" 104 select SUPPORT_SPL 105 select OF_CONTROL 106 select DM 107 108config MACH_PIC32 109 bool "Support Microchip PIC32" 110 select DM 111 select OF_CONTROL 112 imply CMD_DM 113 114config TARGET_BOSTON 115 bool "Support Boston" 116 select DM 117 select DM_SERIAL 118 select MIPS_CM 119 select MIPS_L1_CACHE_SHIFT_6 120 select MIPS_L2_CACHE 121 select OF_BOARD_SETUP 122 select OF_CONTROL 123 select ROM_EXCEPTION_VECTORS 124 select SUPPORTS_BIG_ENDIAN 125 select SUPPORTS_CPU_MIPS32_R1 126 select SUPPORTS_CPU_MIPS32_R2 127 select SUPPORTS_CPU_MIPS32_R6 128 select SUPPORTS_CPU_MIPS64_R1 129 select SUPPORTS_CPU_MIPS64_R2 130 select SUPPORTS_CPU_MIPS64_R6 131 select SUPPORTS_LITTLE_ENDIAN 132 imply CMD_DM 133 134config TARGET_XILFPGA 135 bool "Support Imagination Xilfpga" 136 select DM 137 select DM_ETH 138 select DM_GPIO 139 select DM_SERIAL 140 select MIPS_L1_CACHE_SHIFT_4 141 select OF_CONTROL 142 select ROM_EXCEPTION_VECTORS 143 select SUPPORTS_CPU_MIPS32_R1 144 select SUPPORTS_CPU_MIPS32_R2 145 select SUPPORTS_LITTLE_ENDIAN 146 imply CMD_DM 147 help 148 This supports IMGTEC MIPSfpga platform 149 150endchoice 151 152source "board/imgtec/boston/Kconfig" 153source "board/imgtec/malta/Kconfig" 154source "board/imgtec/xilfpga/Kconfig" 155source "board/qemu-mips/Kconfig" 156source "arch/mips/mach-ath79/Kconfig" 157source "arch/mips/mach-mscc/Kconfig" 158source "arch/mips/mach-bmips/Kconfig" 159source "arch/mips/mach-jz47xx/Kconfig" 160source "arch/mips/mach-pic32/Kconfig" 161source "arch/mips/mach-mtmips/Kconfig" 162 163if MIPS 164 165choice 166 prompt "Endianness selection" 167 help 168 Some MIPS boards can be configured for either little or big endian 169 byte order. These modes require different U-Boot images. In general there 170 is one preferred byteorder for a particular system but some systems are 171 just as commonly used in the one or the other endianness. 172 173config SYS_BIG_ENDIAN 174 bool "Big endian" 175 depends on SUPPORTS_BIG_ENDIAN 176 177config SYS_LITTLE_ENDIAN 178 bool "Little endian" 179 depends on SUPPORTS_LITTLE_ENDIAN 180 181endchoice 182 183choice 184 prompt "CPU selection" 185 default CPU_MIPS32_R2 186 187config CPU_MIPS32_R1 188 bool "MIPS32 Release 1" 189 depends on SUPPORTS_CPU_MIPS32_R1 190 select 32BIT 191 help 192 Choose this option to build an U-Boot for release 1 through 5 of the 193 MIPS32 architecture. 194 195config CPU_MIPS32_R2 196 bool "MIPS32 Release 2" 197 depends on SUPPORTS_CPU_MIPS32_R2 198 select 32BIT 199 help 200 Choose this option to build an U-Boot for release 2 through 5 of the 201 MIPS32 architecture. 202 203config CPU_MIPS32_R6 204 bool "MIPS32 Release 6" 205 depends on SUPPORTS_CPU_MIPS32_R6 206 select 32BIT 207 help 208 Choose this option to build an U-Boot for release 6 or later of the 209 MIPS32 architecture. 210 211config CPU_MIPS64_R1 212 bool "MIPS64 Release 1" 213 depends on SUPPORTS_CPU_MIPS64_R1 214 select 64BIT 215 help 216 Choose this option to build a kernel for release 1 through 5 of the 217 MIPS64 architecture. 218 219config CPU_MIPS64_R2 220 bool "MIPS64 Release 2" 221 depends on SUPPORTS_CPU_MIPS64_R2 222 select 64BIT 223 help 224 Choose this option to build a kernel for release 2 through 5 of the 225 MIPS64 architecture. 226 227config CPU_MIPS64_R6 228 bool "MIPS64 Release 6" 229 depends on SUPPORTS_CPU_MIPS64_R6 230 select 64BIT 231 help 232 Choose this option to build a kernel for release 6 or later of the 233 MIPS64 architecture. 234 235endchoice 236 237menu "General setup" 238 239config ROM_EXCEPTION_VECTORS 240 bool "Build U-Boot image with exception vectors" 241 help 242 Enable this to include exception vectors in the U-Boot image. This is 243 required if the U-Boot entry point is equal to the address of the 244 CPU reset exception vector (e.g. U-Boot as ROM loader in Qemu, 245 U-Boot booted from parallel NOR flash). 246 Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL). 247 In that case the image size will be reduced by 0x500 bytes. 248 249config MIPS_CM_BASE 250 hex "MIPS CM GCR Base Address" 251 depends on MIPS_CM 252 default 0x16100000 if TARGET_BOSTON 253 default 0x1fbf8000 254 help 255 The physical base address at which to map the MIPS Coherence Manager 256 Global Configuration Registers (GCRs). This should be set such that 257 the GCRs occupy a region of the physical address space which is 258 otherwise unused, or at minimum that software doesn't need to access. 259 260config MIPS_CACHE_INDEX_BASE 261 hex "Index base address for cache initialisation" 262 default 0x80000000 if CPU_MIPS32 263 default 0xffffffff80000000 if CPU_MIPS64 264 help 265 This is the base address for a memory block, which is used for 266 initialising the cache lines. This is also the base address of a memory 267 block which is used for loading and filling cache lines when 268 SYS_MIPS_CACHE_INIT_RAM_LOAD is selected. 269 Normally this is CKSEG0. If the MIPS system needs to move this block 270 to some SRAM or ScratchPad RAM, adapt this option accordingly. 271 272config MIPS_RELOCATION_TABLE_SIZE 273 hex "Relocation table size" 274 range 0x100 0x10000 275 default "0x8000" 276 ---help--- 277 A table of relocation data will be appended to the U-Boot binary 278 and parsed in relocate_code() to fix up all offsets in the relocated 279 U-Boot. 280 281 This option allows the amount of space reserved for the table to be 282 adjusted in a range from 256 up to 64k. The default is 32k and should 283 be ok in most cases. Reduce this value to shrink the size of U-Boot 284 binary. 285 286 The build will fail and a valid size suggested if this is too small. 287 288 If unsure, leave at the default value. 289 290endmenu 291 292menu "OS boot interface" 293 294config MIPS_BOOT_CMDLINE_LEGACY 295 bool "Hand over legacy command line to Linux kernel" 296 default y 297 help 298 Enable this option if you want U-Boot to hand over the Yamon-style 299 command line to the kernel. All bootargs will be prepared as argc/argv 300 compatible list. The argument count (argc) is stored in register $a0. 301 The address of the argument list (argv) is stored in register $a1. 302 303config MIPS_BOOT_ENV_LEGACY 304 bool "Hand over legacy environment to Linux kernel" 305 default y 306 help 307 Enable this option if you want U-Boot to hand over the Yamon-style 308 environment to the kernel. Information like memory size, initrd 309 address and size will be prepared as zero-terminated key/value list. 310 The address of the environment is stored in register $a2. 311 312config MIPS_BOOT_FDT 313 bool "Hand over a flattened device tree to Linux kernel" 314 default n 315 help 316 Enable this option if you want U-Boot to hand over a flattened 317 device tree to the kernel. According to UHI register $a0 will be set 318 to -2 and the FDT address is stored in $a1. 319 320endmenu 321 322config SUPPORTS_BIG_ENDIAN 323 bool 324 325config SUPPORTS_LITTLE_ENDIAN 326 bool 327 328config SUPPORTS_CPU_MIPS32_R1 329 bool 330 331config SUPPORTS_CPU_MIPS32_R2 332 bool 333 334config SUPPORTS_CPU_MIPS32_R6 335 bool 336 337config SUPPORTS_CPU_MIPS64_R1 338 bool 339 340config SUPPORTS_CPU_MIPS64_R2 341 bool 342 343config SUPPORTS_CPU_MIPS64_R6 344 bool 345 346config CPU_MIPS32 347 bool 348 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6 349 350config CPU_MIPS64 351 bool 352 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6 353 354config MIPS_TUNE_4KC 355 bool 356 357config MIPS_TUNE_14KC 358 bool 359 360config MIPS_TUNE_24KC 361 bool 362 363config MIPS_TUNE_34KC 364 bool 365 366config MIPS_TUNE_74KC 367 bool 368 369config 32BIT 370 bool 371 372config 64BIT 373 bool 374 375config SWAP_IO_SPACE 376 bool 377 378config SYS_MIPS_CACHE_INIT_RAM_LOAD 379 bool 380 381config MIPS_INIT_STACK_IN_SRAM 382 bool 383 default n 384 help 385 Select this if the initial stack frame could be setup in SRAM. 386 Normally the initial stack frame is set up in DRAM which is often 387 only available after lowlevel_init. With this option the initial 388 stack frame and the early C environment is set up before 389 lowlevel_init. Thus lowlevel_init does not need to be implemented 390 in assembler. 391 392config SYS_DCACHE_SIZE 393 int 394 default 0 395 help 396 The total size of the L1 Dcache, if known at compile time. 397 398config SYS_DCACHE_LINE_SIZE 399 int 400 default 0 401 help 402 The size of L1 Dcache lines, if known at compile time. 403 404config SYS_ICACHE_SIZE 405 int 406 default 0 407 help 408 The total size of the L1 ICache, if known at compile time. 409 410config SYS_ICACHE_LINE_SIZE 411 int 412 default 0 413 help 414 The size of L1 Icache lines, if known at compile time. 415 416config SYS_SCACHE_LINE_SIZE 417 int 418 default 0 419 help 420 The size of L2 cache lines, if known at compile time. 421 422 423config SYS_CACHE_SIZE_AUTO 424 def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \ 425 SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0 && \ 426 SYS_SCACHE_LINE_SIZE = 0 427 help 428 Select this (or let it be auto-selected by not defining any cache 429 sizes) in order to allow U-Boot to automatically detect the sizes 430 of caches at runtime. This has a small cost in code size & runtime 431 so if you know the cache configuration for your system at compile 432 time it would be beneficial to configure it. 433 434config MIPS_L1_CACHE_SHIFT_4 435 bool 436 437config MIPS_L1_CACHE_SHIFT_5 438 bool 439 440config MIPS_L1_CACHE_SHIFT_6 441 bool 442 443config MIPS_L1_CACHE_SHIFT_7 444 bool 445 446config MIPS_L1_CACHE_SHIFT 447 int 448 default "7" if MIPS_L1_CACHE_SHIFT_7 449 default "6" if MIPS_L1_CACHE_SHIFT_6 450 default "5" if MIPS_L1_CACHE_SHIFT_5 451 default "4" if MIPS_L1_CACHE_SHIFT_4 452 default "5" 453 454config MIPS_L2_CACHE 455 bool 456 help 457 Select this if your system includes an L2 cache and you want U-Boot 458 to initialise & maintain it. 459 460config DYNAMIC_IO_PORT_BASE 461 bool 462 463config MIPS_CM 464 bool 465 help 466 Select this if your system contains a MIPS Coherence Manager and you 467 wish U-Boot to configure it or make use of it to retrieve system 468 information such as cache configuration. 469 470config MIPS_INSERT_BOOT_CONFIG 471 bool 472 default n 473 help 474 Enable this to insert some board-specific boot configuration in 475 the U-Boot binary at offset 0x10. 476 477config MIPS_BOOT_CONFIG_WORD0 478 hex 479 depends on MIPS_INSERT_BOOT_CONFIG 480 default 0x420 if TARGET_MALTA 481 default 0x0 482 help 483 Value which is inserted as boot config word 0. 484 485config MIPS_BOOT_CONFIG_WORD1 486 hex 487 depends on MIPS_INSERT_BOOT_CONFIG 488 default 0x0 489 help 490 Value which is inserted as boot config word 1. 491 492endif 493 494endmenu 495