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1#
2# I2C subsystem configuration
3#
4
5menu "I2C support"
6
7config DM_I2C
8	bool "Enable Driver Model for I2C drivers"
9	depends on DM
10	help
11	  Enable driver model for I2C. The I2C uclass interface: probe, read,
12	  write and speed, is implemented with the bus drivers operations,
13	  which provide methods for bus setting and data transfer. Each chip
14	  device (bus child) info is kept as parent platdata. The interface
15	  is defined in include/i2c.h.
16
17config I2C_CROS_EC_TUNNEL
18	tristate "Chrome OS EC tunnel I2C bus"
19	depends on CROS_EC
20	help
21	  This provides an I2C bus that will tunnel i2c commands through to
22	  the other side of the Chrome OS EC to the I2C bus connected there.
23	  This will work whatever the interface used to talk to the EC (SPI,
24	  I2C or LPC). Some Chromebooks use this when the hardware design
25	  does not allow direct access to the main PMIC from the AP.
26
27config I2C_CROS_EC_LDO
28	bool "Provide access to LDOs on the Chrome OS EC"
29	depends on CROS_EC
30	---help---
31	On many Chromebooks the main PMIC is inaccessible to the AP. This is
32	often dealt with by using an I2C pass-through interface provided by
33	the EC. On some unfortunate models (e.g. Spring) the pass-through
34	is not available, and an LDO message is available instead. This
35	option enables a driver which provides very basic access to those
36	regulators, via the EC. We implement this as an I2C bus	which
37	emulates just the TPS65090 messages we know about. This is done to
38	avoid duplicating the logic in the TPS65090 regulator driver for
39	enabling/disabling an LDO.
40
41config I2C_SET_DEFAULT_BUS_NUM
42	bool "Set default I2C bus number"
43	depends on DM_I2C
44	help
45	  Set default number of I2C bus to be accessed. This option provides
46	  behaviour similar to old (i.e. pre DM) I2C bus driver.
47
48config I2C_DEFAULT_BUS_NUMBER
49	hex "I2C default bus number"
50	depends on I2C_SET_DEFAULT_BUS_NUM
51	default 0x0
52	help
53	  Number of default I2C bus to use
54
55config DM_I2C_GPIO
56	bool "Enable Driver Model for software emulated I2C bus driver"
57	depends on DM_I2C && DM_GPIO
58	help
59	  Enable the i2c bus driver emulation by using the GPIOs. The bus GPIO
60	  configuration is given by the device tree. Kernel-style device tree
61	  bindings are supported.
62	  Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt
63
64config SYS_I2C_AT91
65	bool "Atmel I2C driver"
66	depends on DM_I2C && ARCH_AT91
67	help
68	  Add support for the Atmel I2C driver. A serious problem is that there
69	  is no documented way to issue repeated START conditions for more than
70	  two messages, as needed to support combined I2C messages. Use the
71	  i2c-gpio driver unless your system can cope with this limitation.
72	  Binding info: doc/device-tree-bindings/i2c/i2c-at91.txt
73
74config SYS_I2C_FSL
75       bool "Freescale I2C bus driver"
76       depends on DM_I2C
77       help
78	  Add support for Freescale I2C busses as used on MPC8240, MPC8245, and
79	  MPC85xx processors.
80
81config SYS_I2C_CADENCE
82	tristate "Cadence I2C Controller"
83	depends on DM_I2C && (ARCH_ZYNQ || ARM64)
84	help
85	  Say yes here to select Cadence I2C Host Controller. This controller is
86	  e.g. used by Xilinx Zynq.
87
88config SYS_I2C_DAVINCI
89	bool "Davinci I2C Controller"
90	depends on (ARCH_KEYSTONE || ARCH_DAVINCI)
91	help
92	  Say yes here to add support for Davinci and Keystone I2C controller
93
94config SYS_I2C_DW
95	bool "Designware I2C Controller"
96	default n
97	help
98	  Say yes here to select the Designware I2C Host Controller. This
99	  controller is used in various SoCs, e.g. the ST SPEAr, Altera
100	  SoCFPGA, Synopsys ARC700 and some Intel x86 SoCs.
101
102config SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
103	bool "DW I2C Enable Status Register not supported"
104	depends on SYS_I2C_DW && (TARGET_SPEAR300 || TARGET_SPEAR310 || \
105		TARGET_SPEAR320 || TARGET_SPEAR600 || TARGET_X600)
106	default y
107	help
108	  Some versions of the Designware I2C controller do not support the
109	  enable status register. This config option can be enabled in such
110	  cases.
111
112config SYS_I2C_ASPEED
113	bool "Aspeed I2C Controller"
114	depends on DM_I2C && ARCH_ASPEED
115	help
116	  Say yes here to select Aspeed I2C Host Controller. The driver
117	  supports AST2500 and AST2400 controllers, but is very limited.
118	  Only single master mode is supported and only byte-by-byte
119	  synchronous reads and writes are supported, no Pool Buffers or DMA.
120
121config SYS_I2C_INTEL
122	bool "Intel I2C/SMBUS driver"
123	depends on DM_I2C
124	help
125	  Add support for the Intel SMBUS driver. So far this driver is just
126	  a stub which perhaps some basic init. There is no implementation of
127	  the I2C API meaning that any I2C operations will immediately fail
128	  for now.
129
130config SYS_I2C_IMX_LPI2C
131	bool "NXP i.MX LPI2C driver"
132	help
133	  Add support for the NXP i.MX LPI2C driver.
134
135config SYS_I2C_MESON
136	bool "Amlogic Meson I2C driver"
137	depends on DM_I2C && ARCH_MESON
138	help
139	  Add support for the I2C controller available in Amlogic Meson
140	  SoCs. The controller supports programmable bus speed including
141	  standard (100kbits/s) and fast (400kbit/s) speed and allows the
142	  software to define a flexible format of the bit streams. It has an
143	  internal buffer holding up to 8 bytes for transfers and supports
144	  both 7-bit and 10-bit addresses.
145
146config SYS_I2C_MXC
147	bool "NXP MXC I2C driver"
148	help
149	  Add support for the NXP I2C driver. This supports up to four bus
150	  channels and operating on standard mode up to 100 kbits/s and fast
151	  mode up to 400 kbits/s.
152
153# These settings are not used with DM_I2C, however SPL doesn't use
154# DM_I2C even if DM_I2C is enabled, and so might use these settings even
155# when main u-boot does not!
156if SYS_I2C_MXC && (!DM_I2C || SPL)
157config SYS_I2C_MXC_I2C1
158	bool "NXP MXC I2C1"
159	help
160	 Add support for NXP MXC I2C Controller 1.
161	 Required for SoCs which have I2C MXC controller 1 eg LS1088A, LS2080A
162
163config SYS_I2C_MXC_I2C2
164	bool "NXP MXC I2C2"
165	help
166	 Add support for NXP MXC I2C Controller 2.
167	 Required for SoCs which have I2C MXC controller 2 eg LS1088A, LS2080A
168
169config SYS_I2C_MXC_I2C3
170	bool "NXP MXC I2C3"
171	help
172	 Add support for NXP MXC I2C Controller 3.
173	 Required for SoCs which have I2C MXC controller 3 eg LS1088A, LS2080A
174
175config SYS_I2C_MXC_I2C4
176	bool "NXP MXC I2C4"
177	help
178	 Add support for NXP MXC I2C Controller 4.
179	 Required for SoCs which have I2C MXC controller 4 eg LS1088A, LS2080A
180
181config SYS_I2C_MXC_I2C5
182	bool "NXP MXC I2C5"
183	help
184	 Add support for NXP MXC I2C Controller 5.
185	 Required for SoCs which have I2C MXC controller 5 eg LX2160A
186
187config SYS_I2C_MXC_I2C6
188	bool "NXP MXC I2C6"
189	help
190	 Add support for NXP MXC I2C Controller 6.
191	 Required for SoCs which have I2C MXC controller 6 eg LX2160A
192
193config SYS_I2C_MXC_I2C7
194	bool "NXP MXC I2C7"
195	help
196	 Add support for NXP MXC I2C Controller 7.
197	 Required for SoCs which have I2C MXC controller 7 eg LX2160A
198
199config SYS_I2C_MXC_I2C8
200	bool "NXP MXC I2C8"
201	help
202	 Add support for NXP MXC I2C Controller 8.
203	 Required for SoCs which have I2C MXC controller 8 eg LX2160A
204endif
205
206if SYS_I2C_MXC_I2C1
207config SYS_MXC_I2C1_SPEED
208	int "I2C Channel 1 speed"
209	default 40000000 if TARGET_LS2080A_SIMU || TARGET_LS2080A_EMU
210	default 100000
211	help
212	 MXC I2C Channel 1 speed
213
214config SYS_MXC_I2C1_SLAVE
215	int "I2C1 Slave"
216	default 0
217	help
218	 MXC I2C1 Slave
219endif
220
221if SYS_I2C_MXC_I2C2
222config SYS_MXC_I2C2_SPEED
223	int "I2C Channel 2 speed"
224	default 40000000 if TARGET_LS2080A_SIMU || TARGET_LS2080A_EMU
225	default 100000
226	help
227	 MXC I2C Channel 2 speed
228
229config SYS_MXC_I2C2_SLAVE
230	int "I2C2 Slave"
231	default 0
232	help
233	 MXC I2C2 Slave
234endif
235
236if SYS_I2C_MXC_I2C3
237config SYS_MXC_I2C3_SPEED
238	int "I2C Channel 3 speed"
239	default 100000
240	help
241	 MXC I2C Channel 3 speed
242
243config SYS_MXC_I2C3_SLAVE
244	int "I2C3 Slave"
245	default 0
246	help
247	 MXC I2C3 Slave
248endif
249
250if SYS_I2C_MXC_I2C4
251config SYS_MXC_I2C4_SPEED
252	int "I2C Channel 4 speed"
253	default 100000
254	help
255	 MXC I2C Channel 4 speed
256
257config SYS_MXC_I2C4_SLAVE
258	int "I2C4 Slave"
259	default 0
260	help
261	 MXC I2C4 Slave
262endif
263
264if SYS_I2C_MXC_I2C5
265config SYS_MXC_I2C5_SPEED
266	int "I2C Channel 5 speed"
267	default 100000
268	help
269	 MXC I2C Channel 5 speed
270
271config SYS_MXC_I2C5_SLAVE
272	int "I2C5 Slave"
273	default 0
274	help
275	 MXC I2C5 Slave
276endif
277
278if SYS_I2C_MXC_I2C6
279config SYS_MXC_I2C6_SPEED
280	int "I2C Channel 6 speed"
281	default 100000
282	help
283	 MXC I2C Channel 6 speed
284
285config SYS_MXC_I2C6_SLAVE
286	int "I2C6 Slave"
287	default 0
288	help
289	 MXC I2C6 Slave
290endif
291
292if SYS_I2C_MXC_I2C7
293config SYS_MXC_I2C7_SPEED
294	int "I2C Channel 7 speed"
295	default 100000
296	help
297	 MXC I2C Channel 7 speed
298
299config SYS_MXC_I2C7_SLAVE
300	int "I2C7 Slave"
301	default 0
302	help
303	 MXC I2C7 Slave
304endif
305
306if SYS_I2C_MXC_I2C8
307config SYS_MXC_I2C8_SPEED
308	int "I2C Channel 8 speed"
309	default 100000
310	help
311	 MXC I2C Channel 8 speed
312
313config SYS_MXC_I2C8_SLAVE
314	int "I2C8 Slave"
315	default 0
316	help
317	 MXC I2C8 Slave
318endif
319
320config SYS_I2C_OMAP24XX
321	bool "TI OMAP2+ I2C driver"
322	depends on ARCH_OMAP2PLUS || ARCH_K3
323	help
324	  Add support for the OMAP2+ I2C driver.
325
326if SYS_I2C_OMAP24XX
327config SYS_OMAP24_I2C_SLAVE
328	int "I2C Slave addr channel 0"
329	default 1
330	help
331	  OMAP24xx I2C Slave address channel 0
332
333config SYS_OMAP24_I2C_SPEED
334	int "I2C Slave channel 0 speed"
335	default 100000
336	help
337	  OMAP24xx Slave speed channel 0
338endif
339
340config SYS_I2C_RCAR_I2C
341	bool "Renesas RCar I2C driver"
342	depends on (RCAR_GEN3 || RCAR_GEN2) && DM_I2C
343	help
344	  Support for Renesas RCar I2C controller.
345
346config SYS_I2C_RCAR_IIC
347	bool "Renesas RCar Gen3 IIC driver"
348	depends on (RCAR_GEN3 || RCAR_GEN2) && DM_I2C
349	help
350	  Support for Renesas RCar Gen3 IIC controller.
351
352config SYS_I2C_ROCKCHIP
353	bool "Rockchip I2C driver"
354	depends on DM_I2C
355	help
356	  Add support for the Rockchip I2C driver. This is used with various
357	  Rockchip parts such as RK3126, RK3128, RK3036 and RK3288. All chips
358	  have several I2C ports and all are provided, controlled by the
359	  device tree.
360
361config SYS_I2C_SANDBOX
362	bool "Sandbox I2C driver"
363	depends on SANDBOX && DM_I2C
364	help
365	  Enable I2C support for sandbox. This is an emulation of a real I2C
366	  bus. Devices can be attached to the bus using the device tree
367	  which specifies the driver to use.  See sandbox.dts as an example.
368
369config SYS_I2C_S3C24X0
370	bool "Samsung I2C driver"
371	depends on ARCH_EXYNOS4 && DM_I2C
372	help
373	  Support for Samsung I2C controller as Samsung SoCs.
374
375config SYS_I2C_STM32F7
376	bool "STMicroelectronics STM32F7 I2C support"
377	depends on (STM32F7 || STM32H7 || ARCH_STM32MP) && DM_I2C
378	help
379	  Enable this option to add support for STM32 I2C controller
380	  introduced with STM32F7/H7 SoCs. This I2C controller supports :
381	   _ Slave and master modes
382	   _ Multimaster capability
383	   _ Standard-mode (up to 100 kHz)
384	   _ Fast-mode (up to 400 kHz)
385	   _ Fast-mode Plus (up to 1 MHz)
386	   _ 7-bit and 10-bit addressing mode
387	   _ Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask)
388	   _ All 7-bit addresses acknowledge mode
389	   _ General call
390	   _ Programmable setup and hold times
391	   _ Easy to use event management
392	   _ Optional clock stretching
393	   _ Software reset
394
395config SYS_I2C_TEGRA
396	bool "NVIDIA Tegra internal I2C controller"
397	depends on TEGRA
398	help
399	  Support for NVIDIA I2C controller available in Tegra SoCs.
400
401config SYS_I2C_UNIPHIER
402	bool "UniPhier I2C driver"
403	depends on ARCH_UNIPHIER && DM_I2C
404	default y
405	help
406	  Support for UniPhier I2C controller driver.  This I2C controller
407	  is used on PH1-LD4, PH1-sLD8 or older UniPhier SoCs.
408
409config SYS_I2C_UNIPHIER_F
410	bool "UniPhier FIFO-builtin I2C driver"
411	depends on ARCH_UNIPHIER && DM_I2C
412	default y
413	help
414	  Support for UniPhier FIFO-builtin I2C controller driver.
415	  This I2C controller is used on PH1-Pro4 or newer UniPhier SoCs.
416
417config SYS_I2C_VERSATILE
418	bool "Arm Ltd Versatile I2C bus driver"
419	depends on DM_I2C && (TARGET_VEXPRESS_CA15_TC2 || TARGET_VEXPRESS64_JUNO)
420	help
421	  Add support for the Arm Ltd Versatile Express I2C driver. The I2C host
422	  controller is present in the development boards manufactured by Arm Ltd.
423
424config SYS_I2C_MVTWSI
425	bool "Marvell I2C driver"
426	depends on DM_I2C
427	help
428	  Support for Marvell I2C controllers as used on the orion5x and
429	  kirkwood SoC families.
430
431config TEGRA186_BPMP_I2C
432	bool "Enable Tegra186 BPMP-based I2C driver"
433	depends on TEGRA186_BPMP
434	help
435	  Support for Tegra I2C controllers managed by the BPMP (Boot and
436	  Power Management Processor). On Tegra186, some I2C controllers are
437	  directly controlled by the main CPU, whereas others are controlled
438	  by the BPMP, and can only be accessed by the main CPU via IPC
439	  requests to the BPMP. This driver covers the latter case.
440
441config SYS_I2C_BUS_MAX
442	int "Max I2C busses"
443	depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_SOCFPGA
444	default 2 if TI816X
445	default 3 if OMAP34XX || AM33XX || AM43XX || ARCH_KEYSTONE
446	default 4 if ARCH_SOCFPGA || OMAP44XX || TI814X
447	default 5 if OMAP54XX
448	help
449	  Define the maximum number of available I2C buses.
450
451config SYS_I2C_XILINX_XIIC
452	bool "Xilinx AXI I2C driver"
453	depends on DM_I2C
454	help
455	  Support for Xilinx AXI I2C controller.
456
457config SYS_I2C_IHS
458        bool "gdsys IHS I2C driver"
459        depends on DM_I2C
460        help
461          Support for gdsys IHS I2C driver on FPGA bus.
462
463source "drivers/i2c/muxes/Kconfig"
464
465endmenu
466