1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc. 4 */ 5 6 /* 7 * mpc8544ds board configuration file 8 * 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_PCI1 1 /* PCI controller 1 */ 14 #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ 15 #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ 16 #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */ 17 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 18 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 19 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 20 21 #define CONFIG_ENV_OVERWRITE 22 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 23 24 #ifndef __ASSEMBLY__ 25 extern unsigned long get_board_sys_clk(unsigned long dummy); 26 #endif 27 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ 28 29 /* 30 * These can be toggled for performance analysis, otherwise use default. 31 */ 32 #define CONFIG_L2_CACHE /* toggle L2 cache */ 33 #define CONFIG_BTB /* toggle branch predition */ 34 35 /* 36 * Only possible on E500 Version 2 or newer cores. 37 */ 38 #define CONFIG_ENABLE_36BIT_PHYS 1 39 40 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 41 #define CONFIG_SYS_MEMTEST_END 0x00400000 42 43 #define CONFIG_SYS_CCSRBAR 0xe0000000 44 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 45 46 /* DDR Setup */ 47 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 48 #define CONFIG_DDR_SPD 49 50 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 51 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 52 53 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 54 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 55 #define CONFIG_VERY_BIG_RAM 56 57 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 58 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 59 60 /* I2C addresses of SPD EEPROMs */ 61 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ 62 63 /* Make sure required options are set */ 64 #ifndef CONFIG_SPD_EEPROM 65 #error ("CONFIG_SPD_EEPROM is required") 66 #endif 67 68 #undef CONFIG_CLOCKS_IN_MHZ 69 70 /* 71 * Memory map 72 * 73 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 74 * 75 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 76 * 77 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 78 * 79 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable 80 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 81 * 82 * Localbus cacheable 83 * 84 * 0xf000_0000 0xf3ff_ffff SDRAM 64M Cacheable 85 * 0xf401_0000 0xf401_3fff L1 for stack 4K Cacheable TLB0 86 * 87 * Localbus non-cacheable 88 * 89 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M non-cacheable 90 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable 91 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable 92 * 93 */ 94 95 /* 96 * Local Bus Definitions 97 */ 98 #define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* boot TLB */ 99 100 #define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */ 101 102 #define CONFIG_SYS_BR0_PRELIM 0xff801001 103 #define CONFIG_SYS_BR1_PRELIM 0xfe801001 104 105 #define CONFIG_SYS_OR0_PRELIM 0xff806e65 106 #define CONFIG_SYS_OR1_PRELIM 0xff806e65 107 108 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} 109 110 #define CONFIG_SYS_FLASH_QUIET_TEST 111 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 112 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 113 #undef CONFIG_SYS_FLASH_CHECKSUM 114 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 115 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 116 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 117 118 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 119 120 #define CONFIG_SYS_FLASH_EMPTY_INFO 121 122 #define CONFIG_SYS_LBC_NONCACHE_BASE 0xf8000000 123 124 #define CONFIG_SYS_BR2_PRELIM 0xf8201001 /* port size 16bit */ 125 #define CONFIG_SYS_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/ 126 127 #define CONFIG_SYS_BR3_PRELIM 0xf8100801 /* port size 8bit */ 128 #define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ 129 130 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 131 #define PIXIS_BASE 0xf8100000 /* PIXIS registers */ 132 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 133 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 134 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 135 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 136 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch 137 * register */ 138 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 139 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 140 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 141 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 142 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 143 #define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */ 144 #define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */ 145 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 146 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 147 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 148 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 149 #define PIXIS_VSPEED2 0x1d /* VELA VSpeed 2 */ 150 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ 151 #define PIXIS_VSPEED2_TSEC1SER 0x2 152 #define PIXIS_VSPEED2_TSEC3SER 0x1 153 #define PIXIS_VCFGEN1_TSEC1SER 0x20 154 #define PIXIS_VCFGEN1_TSEC3SER 0x40 155 #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER|PIXIS_VSPEED2_TSEC3SER) 156 #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER|PIXIS_VCFGEN1_TSEC3SER) 157 158 #define CONFIG_SYS_INIT_RAM_LOCK 1 159 #define CONFIG_SYS_INIT_RAM_ADDR 0xf4010000 /* Initial L1 address */ 160 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 161 162 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 163 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 164 165 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 166 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 167 168 /* Serial Port - controlled on board with jumper J8 169 * open - index 2 170 * shorted - index 1 171 */ 172 #define CONFIG_SYS_NS16550_SERIAL 173 #define CONFIG_SYS_NS16550_REG_SIZE 1 174 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 175 176 #define CONFIG_SYS_BAUDRATE_TABLE \ 177 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 178 179 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 180 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 181 182 /* I2C */ 183 #define CONFIG_SYS_I2C 184 #define CONFIG_SYS_I2C_FSL 185 #define CONFIG_SYS_FSL_I2C_SPEED 400000 186 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 187 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100 188 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 189 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 190 191 /* 192 * General PCI 193 * Memory space is mapped 1-1, but I/O space must start from 0. 194 */ 195 #define CONFIG_SYS_PCIE_VIRT 0x80000000 /* 1G PCIE TLB */ 196 #define CONFIG_SYS_PCIE_PHYS 0x80000000 /* 1G PCIE TLB */ 197 #define CONFIG_SYS_PCI_VIRT 0xc0000000 /* 512M PCI TLB */ 198 #define CONFIG_SYS_PCI_PHYS 0xc0000000 /* 512M PCI TLB */ 199 200 #define CONFIG_SYS_PCI1_MEM_VIRT 0xc0000000 201 #define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000 202 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc0000000 203 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 204 #define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000 205 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 206 #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000 207 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ 208 209 /* controller 2, Slot 1, tgtid 1, Base address 9000 */ 210 #define CONFIG_SYS_PCIE2_NAME "Slot 1" 211 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x80000000 212 #define CONFIG_SYS_PCIE2_MEM_BUS 0x80000000 213 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x80000000 214 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 215 #define CONFIG_SYS_PCIE2_IO_VIRT 0xe1010000 216 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 217 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe1010000 218 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 219 220 /* controller 1, Slot 2,tgtid 2, Base address a000 */ 221 #define CONFIG_SYS_PCIE1_NAME "Slot 2" 222 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 223 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 224 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 225 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 226 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe1020000 227 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 228 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe1020000 229 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 230 231 /* controller 3, direct to uli, tgtid 3, Base address b000 */ 232 #define CONFIG_SYS_PCIE3_NAME "ULI" 233 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 234 #define CONFIG_SYS_PCIE3_MEM_BUS 0xb0000000 235 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xb0000000 236 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x00100000 /* 1M */ 237 #define CONFIG_SYS_PCIE3_IO_VIRT 0xb0100000 /* reuse mem LAW */ 238 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 239 #define CONFIG_SYS_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */ 240 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00100000 /* 1M */ 241 #define CONFIG_SYS_PCIE3_MEM_VIRT2 0xb0200000 242 #define CONFIG_SYS_PCIE3_MEM_BUS2 0xb0200000 243 #define CONFIG_SYS_PCIE3_MEM_PHYS2 0xb0200000 244 #define CONFIG_SYS_PCIE3_MEM_SIZE2 0x00200000 /* 1M */ 245 246 #if defined(CONFIG_PCI) 247 248 /*PCIE video card used*/ 249 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT 250 251 /*PCI video card used*/ 252 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ 253 254 /* video */ 255 256 #if defined(CONFIG_VIDEO) 257 #define CONFIG_BIOSEMU 258 #define CONFIG_ATI_RADEON_FB 259 #define CONFIG_VIDEO_LOGO 260 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 261 #endif 262 263 #undef CONFIG_EEPRO100 264 #undef CONFIG_TULIP 265 266 #ifndef CONFIG_PCI_PNP 267 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS 268 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS 269 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 270 #endif 271 272 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 273 274 #ifdef CONFIG_SCSI_AHCI 275 #define CONFIG_SATA_ULI5288 276 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 277 #define CONFIG_SYS_SCSI_MAX_LUN 1 278 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 279 #endif /* CONFIG_SCSI_AHCI */ 280 281 #endif /* CONFIG_PCI */ 282 283 #if defined(CONFIG_TSEC_ENET) 284 285 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 286 #define CONFIG_TSEC1 1 287 #define CONFIG_TSEC1_NAME "eTSEC1" 288 #define CONFIG_TSEC3 1 289 #define CONFIG_TSEC3_NAME "eTSEC3" 290 291 #define CONFIG_PIXIS_SGMII_CMD 292 #define CONFIG_FSL_SGMII_RISER 1 293 #define SGMII_RISER_PHY_OFFSET 0x1c 294 295 #define TSEC1_PHY_ADDR 0 296 #define TSEC3_PHY_ADDR 1 297 298 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 299 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 300 301 #define TSEC1_PHYIDX 0 302 #define TSEC3_PHYIDX 0 303 304 #define CONFIG_ETHPRIME "eTSEC1" 305 #endif /* CONFIG_TSEC_ENET */ 306 307 /* 308 * Environment 309 */ 310 311 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 312 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 313 314 /* 315 * BOOTP options 316 */ 317 #define CONFIG_BOOTP_BOOTFILESIZE 318 319 /* 320 * USB 321 */ 322 323 #ifdef CONFIG_USB_EHCI_HCD 324 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 325 #define CONFIG_PCI_EHCI_DEVICE 0 326 #endif 327 328 #undef CONFIG_WATCHDOG /* watchdog disabled */ 329 330 /* 331 * Miscellaneous configurable options 332 */ 333 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 334 335 /* 336 * For booting Linux, the board info and command line data 337 * have to be in the first 64 MB of memory, since this is 338 * the maximum mapped by the Linux kernel during initialization. 339 */ 340 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 341 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 342 343 #if defined(CONFIG_CMD_KGDB) 344 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 345 #endif 346 347 /* 348 * Environment Configuration 349 */ 350 351 /* The mac addresses for all ethernet interface */ 352 #if defined(CONFIG_TSEC_ENET) 353 #define CONFIG_HAS_ETH0 354 #define CONFIG_HAS_ETH1 355 #endif 356 357 #define CONFIG_IPADDR 192.168.1.251 358 359 #define CONFIG_HOSTNAME "8544ds_unknown" 360 #define CONFIG_ROOTPATH "/nfs/mpc85xx" 361 #define CONFIG_BOOTFILE "8544ds/uImage.uboot" 362 #define CONFIG_UBOOTPATH 8544ds/u-boot.bin /* TFTP server */ 363 364 #define CONFIG_SERVERIP 192.168.1.1 365 #define CONFIG_GATEWAYIP 192.168.1.1 366 #define CONFIG_NETMASK 255.255.0.0 367 368 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ 369 370 #define CONFIG_EXTRA_ENV_SETTINGS \ 371 "netdev=eth0\0" \ 372 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 373 "tftpflash=tftpboot $loadaddr $uboot; " \ 374 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 375 " +$filesize; " \ 376 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 377 " +$filesize; " \ 378 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 379 " $filesize; " \ 380 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 381 " +$filesize; " \ 382 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 383 " $filesize\0" \ 384 "consoledev=ttyS0\0" \ 385 "ramdiskaddr=2000000\0" \ 386 "ramdiskfile=8544ds/ramdisk.uboot\0" \ 387 "fdtaddr=1e00000\0" \ 388 "fdtfile=8544ds/mpc8544ds.dtb\0" \ 389 "bdev=sda3\0" 390 391 #define CONFIG_NFSBOOTCOMMAND \ 392 "setenv bootargs root=/dev/nfs rw " \ 393 "nfsroot=$serverip:$rootpath " \ 394 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 395 "console=$consoledev,$baudrate $othbootargs;" \ 396 "tftp $loadaddr $bootfile;" \ 397 "tftp $fdtaddr $fdtfile;" \ 398 "bootm $loadaddr - $fdtaddr" 399 400 #define CONFIG_RAMBOOTCOMMAND \ 401 "setenv bootargs root=/dev/ram rw " \ 402 "console=$consoledev,$baudrate $othbootargs;" \ 403 "tftp $ramdiskaddr $ramdiskfile;" \ 404 "tftp $loadaddr $bootfile;" \ 405 "tftp $fdtaddr $fdtfile;" \ 406 "bootm $loadaddr $ramdiskaddr $fdtaddr" 407 408 #define CONFIG_BOOTCOMMAND \ 409 "setenv bootargs root=/dev/$bdev rw " \ 410 "console=$consoledev,$baudrate $othbootargs;" \ 411 "tftp $loadaddr $bootfile;" \ 412 "tftp $fdtaddr $fdtfile;" \ 413 "bootm $loadaddr - $fdtaddr" 414 415 #endif /* __CONFIG_H */ 416