1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2009-2011 Freescale Semiconductor, Inc. 4 */ 5 6 /* 7 * mpc8569mds board configuration file 8 */ 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #define CONFIG_SYS_SRIO 13 #define CONFIG_SRIO1 /* SRIO port 1 */ 14 15 #define CONFIG_PCIE1 1 /* PCIE controller */ 16 #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ 17 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 18 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 19 #define CONFIG_ENV_OVERWRITE 20 21 #ifndef __ASSEMBLY__ 22 extern unsigned long get_clock_freq(void); 23 #endif 24 /* Replace a call to get_clock_freq (after it is implemented)*/ 25 #define CONFIG_SYS_CLK_FREQ 66666666 26 #define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ 27 28 #ifdef CONFIG_ATM 29 #define CONFIG_PQ_MDS_PIB 30 #define CONFIG_PQ_MDS_PIB_ATM 31 #endif 32 33 /* 34 * These can be toggled for performance analysis, otherwise use default. 35 */ 36 #define CONFIG_L2_CACHE /* toggle L2 cache */ 37 #define CONFIG_BTB /* toggle branch predition */ 38 39 #ifndef CONFIG_SYS_MONITOR_BASE 40 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 41 #endif 42 43 /* 44 * Only possible on E500 Version 2 or newer cores. 45 */ 46 #define CONFIG_ENABLE_36BIT_PHYS 1 47 48 #define CONFIG_HWCONFIG 49 50 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 51 #define CONFIG_SYS_MEMTEST_END 0x00400000 52 53 /* 54 * Config the L2 Cache as L2 SRAM 55 */ 56 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 57 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 58 #define CONFIG_SYS_L2_SIZE (512 << 10) 59 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 60 61 #define CONFIG_SYS_CCSRBAR 0xe0000000 62 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 63 64 #if defined(CONFIG_NAND_SPL) 65 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 66 #endif 67 68 /* DDR Setup */ 69 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 70 #define CONFIG_DDR_SPD 71 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 72 73 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 74 75 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 76 /* DDR is system memory*/ 77 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 78 79 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 80 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 81 82 /* I2C addresses of SPD EEPROMs */ 83 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 84 85 /* These are used when DDR doesn't use SPD. */ 86 #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1024MB */ 87 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F 88 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 89 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 90 #define CONFIG_SYS_DDR_TIMING_0 0x00330004 91 #define CONFIG_SYS_DDR_TIMING_1 0x6F6B4644 92 #define CONFIG_SYS_DDR_TIMING_2 0x002888D0 93 #define CONFIG_SYS_DDR_SDRAM_CFG 0x47000000 94 #define CONFIG_SYS_DDR_SDRAM_CFG_2 0x04401040 95 #define CONFIG_SYS_DDR_SDRAM_MODE 0x40401521 96 #define CONFIG_SYS_DDR_SDRAM_MODE_2 0x8000C000 97 #define CONFIG_SYS_DDR_SDRAM_INTERVAL 0x03E00000 98 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 99 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x01000000 100 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 101 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 102 #define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 103 #define CONFIG_SYS_DDR_WRLVL_CNTL 0x0655A604 104 #define CONFIG_SYS_DDR_CDR_1 0x80040000 105 #define CONFIG_SYS_DDR_CDR_2 0x00000000 106 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 107 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 108 #define CONFIG_SYS_DDR_CONTROL 0xc7000000 /* Type = DDR3 */ 109 #define CONFIG_SYS_DDR_CONTROL2 0x24400000 110 111 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 112 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 113 #define CONFIG_SYS_DDR_SBE 0x00010000 114 115 #undef CONFIG_CLOCKS_IN_MHZ 116 117 /* 118 * Local Bus Definitions 119 */ 120 121 #define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */ 122 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 123 124 #define CONFIG_SYS_BCSR_BASE 0xf8000000 125 #define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE 126 127 /*Chip select 0 - Flash*/ 128 #define CONFIG_FLASH_BR_PRELIM 0xfe000801 129 #define CONFIG_FLASH_OR_PRELIM 0xfe000ff7 130 131 /*Chip select 1 - BCSR*/ 132 #define CONFIG_SYS_BR1_PRELIM 0xf8000801 133 #define CONFIG_SYS_OR1_PRELIM 0xffffe9f7 134 135 /*Chip select 4 - PIB*/ 136 #define CONFIG_SYS_BR4_PRELIM 0xf8008801 137 #define CONFIG_SYS_OR4_PRELIM 0xffffe9f7 138 139 /*Chip select 5 - PIB*/ 140 #define CONFIG_SYS_BR5_PRELIM 0xf8010801 141 #define CONFIG_SYS_OR5_PRELIM 0xffffe9f7 142 143 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 144 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ 145 #undef CONFIG_SYS_FLASH_CHECKSUM 146 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 147 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 148 149 #undef CONFIG_SYS_RAMBOOT 150 151 #define CONFIG_SYS_FLASH_EMPTY_INFO 152 153 /* Chip select 3 - NAND */ 154 #ifndef CONFIG_NAND_SPL 155 #define CONFIG_SYS_NAND_BASE 0xFC000000 156 #else 157 #define CONFIG_SYS_NAND_BASE 0xFFF00000 158 #endif 159 160 /* NAND boot: 4K NAND loader config */ 161 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 162 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) 163 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) 164 #define CONFIG_SYS_NAND_U_BOOT_START \ 165 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) 166 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) 167 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) 168 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 169 170 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 171 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, } 172 #define CONFIG_SYS_MAX_NAND_DEVICE 1 173 #define CONFIG_NAND_FSL_ELBC 1 174 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 175 #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \ 176 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 177 | BR_PS_8 /* Port Size = 8 bit */ \ 178 | BR_MS_FCM /* MSEL = FCM */ \ 179 | BR_V) /* valid */ 180 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 181 | OR_FCM_CSCT \ 182 | OR_FCM_CST \ 183 | OR_FCM_CHT \ 184 | OR_FCM_SCY_1 \ 185 | OR_FCM_TRLX \ 186 | OR_FCM_EHTR) 187 188 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 189 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 190 #define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 191 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 192 193 #define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */ 194 #define CONFIG_SYS_LBC_LBCR 0x00040000 /* LB config reg */ 195 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 196 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 197 198 #define CONFIG_SYS_INIT_RAM_LOCK 1 199 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 200 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 201 202 #define CONFIG_SYS_GBL_DATA_OFFSET \ 203 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 204 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 205 206 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 207 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 208 209 /* Serial Port */ 210 #define CONFIG_SYS_NS16550_SERIAL 211 #define CONFIG_SYS_NS16550_REG_SIZE 1 212 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 213 #ifdef CONFIG_NAND_SPL 214 #define CONFIG_NS16550_MIN_FUNCTIONS 215 #endif 216 217 #define CONFIG_SYS_BAUDRATE_TABLE \ 218 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 219 220 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 221 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 222 223 /* 224 * I2C 225 */ 226 #define CONFIG_SYS_I2C 227 #define CONFIG_SYS_I2C_FSL 228 #define CONFIG_SYS_FSL_I2C_SPEED 400000 229 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 230 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 231 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 232 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 233 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 234 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 235 236 /* 237 * I2C2 EEPROM 238 */ 239 #define CONFIG_ID_EEPROM 240 #ifdef CONFIG_ID_EEPROM 241 #define CONFIG_SYS_I2C_EEPROM_NXID 242 #endif 243 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 244 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 245 #define CONFIG_SYS_EEPROM_BUS_NUM 1 246 247 #define PLPPAR1_I2C_BIT_MASK 0x0000000F 248 #define PLPPAR1_I2C2_VAL 0x00000000 249 #define PLPPAR1_ESDHC_VAL 0x0000000A 250 #define PLPDIR1_I2C_BIT_MASK 0x0000000F 251 #define PLPDIR1_I2C2_VAL 0x0000000F 252 #define PLPDIR1_ESDHC_VAL 0x00000006 253 #define PLPPAR1_UART0_BIT_MASK 0x00000fc0 254 #define PLPPAR1_ESDHC_4BITS_VAL 0x00000a80 255 #define PLPDIR1_UART0_BIT_MASK 0x00000fc0 256 #define PLPDIR1_ESDHC_4BITS_VAL 0x00000a80 257 258 /* 259 * General PCI 260 * Memory Addresses are mapped 1-1. I/O is mapped from 0 261 */ 262 #define CONFIG_SYS_PCIE1_NAME "Slot" 263 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 264 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 265 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 266 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 267 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 268 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 269 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 270 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ 271 272 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000 273 #define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000 274 #define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS 275 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ 276 277 #ifdef CONFIG_QE 278 /* 279 * QE UEC ethernet configuration 280 */ 281 #define CONFIG_SYS_UCC_RGMII_MODE /* Set UCC work at RGMII by default */ 282 #undef CONFIG_SYS_UCC_RMII_MODE /* Set UCC work at RMII mode */ 283 284 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) 285 #define CONFIG_UEC_ETH 286 #define CONFIG_ETHPRIME "UEC0" 287 #define CONFIG_PHY_MODE_NEED_CHANGE 288 289 #define CONFIG_UEC_ETH1 /* GETH1 */ 290 #define CONFIG_HAS_ETH0 291 292 #ifdef CONFIG_UEC_ETH1 293 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 294 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE 295 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 296 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK12 297 #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH 298 #define CONFIG_SYS_UEC1_PHY_ADDR 7 299 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID 300 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 301 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 302 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 /* CLK16 for RMII */ 303 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 304 #define CONFIG_SYS_UEC1_PHY_ADDR 8 /* 0x8 for RMII */ 305 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 306 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 307 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 308 #endif /* CONFIG_UEC_ETH1 */ 309 310 #define CONFIG_UEC_ETH2 /* GETH2 */ 311 #define CONFIG_HAS_ETH1 312 313 #ifdef CONFIG_UEC_ETH2 314 #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ 315 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE 316 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 317 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK17 318 #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH 319 #define CONFIG_SYS_UEC2_PHY_ADDR 1 320 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID 321 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 322 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 323 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 /* CLK 16 for RMII */ 324 #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH 325 #define CONFIG_SYS_UEC2_PHY_ADDR 0x9 /* 0x9 for RMII */ 326 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 327 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 328 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 329 #endif /* CONFIG_UEC_ETH2 */ 330 331 #define CONFIG_UEC_ETH3 /* GETH3 */ 332 #define CONFIG_HAS_ETH2 333 334 #ifdef CONFIG_UEC_ETH3 335 #define CONFIG_SYS_UEC3_UCC_NUM 2 /* UCC3 */ 336 #define CONFIG_SYS_UEC3_RX_CLK QE_CLK_NONE 337 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 338 #define CONFIG_SYS_UEC3_TX_CLK QE_CLK12 339 #define CONFIG_SYS_UEC3_ETH_TYPE GIGA_ETH 340 #define CONFIG_SYS_UEC3_PHY_ADDR 2 341 #define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID 342 #define CONFIG_SYS_UEC3_INTERFACE_SPEED 1000 343 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 344 #define CONFIG_SYS_UEC3_TX_CLK QE_CLK16 /* CLK_16 for RMII */ 345 #define CONFIG_SYS_UEC3_ETH_TYPE FAST_ETH 346 #define CONFIG_SYS_UEC3_PHY_ADDR 0xA /* 0xA for RMII */ 347 #define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 348 #define CONFIG_SYS_UEC3_INTERFACE_SPEED 100 349 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 350 #endif /* CONFIG_UEC_ETH3 */ 351 352 #define CONFIG_UEC_ETH4 /* GETH4 */ 353 #define CONFIG_HAS_ETH3 354 355 #ifdef CONFIG_UEC_ETH4 356 #define CONFIG_SYS_UEC4_UCC_NUM 3 /* UCC4 */ 357 #define CONFIG_SYS_UEC4_RX_CLK QE_CLK_NONE 358 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 359 #define CONFIG_SYS_UEC4_TX_CLK QE_CLK17 360 #define CONFIG_SYS_UEC4_ETH_TYPE GIGA_ETH 361 #define CONFIG_SYS_UEC4_PHY_ADDR 3 362 #define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID 363 #define CONFIG_SYS_UEC4_INTERFACE_SPEED 1000 364 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 365 #define CONFIG_SYS_UEC4_TX_CLK QE_CLK16 /* CLK16 for RMII */ 366 #define CONFIG_SYS_UEC4_ETH_TYPE FAST_ETH 367 #define CONFIG_SYS_UEC4_PHY_ADDR 0xB /* 0xB for RMII */ 368 #define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 369 #define CONFIG_SYS_UEC4_INTERFACE_SPEED 100 370 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 371 #endif /* CONFIG_UEC_ETH4 */ 372 373 #undef CONFIG_UEC_ETH6 /* GETH6 */ 374 #define CONFIG_HAS_ETH5 375 376 #ifdef CONFIG_UEC_ETH6 377 #define CONFIG_SYS_UEC6_UCC_NUM 5 /* UCC6 */ 378 #define CONFIG_SYS_UEC6_RX_CLK QE_CLK_NONE 379 #define CONFIG_SYS_UEC6_TX_CLK QE_CLK_NONE 380 #define CONFIG_SYS_UEC6_ETH_TYPE GIGA_ETH 381 #define CONFIG_SYS_UEC6_PHY_ADDR 4 382 #define CONFIG_SYS_UEC6_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII 383 #define CONFIG_SYS_UEC6_INTERFACE_SPEED 1000 384 #endif /* CONFIG_UEC_ETH6 */ 385 386 #undef CONFIG_UEC_ETH8 /* GETH8 */ 387 #define CONFIG_HAS_ETH7 388 389 #ifdef CONFIG_UEC_ETH8 390 #define CONFIG_SYS_UEC8_UCC_NUM 7 /* UCC8 */ 391 #define CONFIG_SYS_UEC8_RX_CLK QE_CLK_NONE 392 #define CONFIG_SYS_UEC8_TX_CLK QE_CLK_NONE 393 #define CONFIG_SYS_UEC8_ETH_TYPE GIGA_ETH 394 #define CONFIG_SYS_UEC8_PHY_ADDR 6 395 #define CONFIG_SYS_UEC8_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII 396 #define CONFIG_SYS_UEC8_INTERFACE_SPEED 1000 397 #endif /* CONFIG_UEC_ETH8 */ 398 399 #endif /* CONFIG_QE */ 400 401 #if defined(CONFIG_PCI) 402 #undef CONFIG_EEPRO100 403 #undef CONFIG_TULIP 404 405 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 406 407 #endif /* CONFIG_PCI */ 408 409 /* 410 * Environment 411 */ 412 413 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 414 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 415 416 /* QE microcode/firmware address */ 417 #define CONFIG_SYS_QE_FW_ADDR 0xfff00000 418 419 /* 420 * BOOTP options 421 */ 422 #define CONFIG_BOOTP_BOOTFILESIZE 423 424 #undef CONFIG_WATCHDOG /* watchdog disabled */ 425 426 #ifdef CONFIG_MMC 427 #define CONFIG_FSL_ESDHC_PIN_MUX 428 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 429 #endif 430 431 /* 432 * Miscellaneous configurable options 433 */ 434 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 435 #if defined(CONFIG_CMD_KGDB) 436 #define CONFIG_SYS_CBSIZE 2048 /* Console I/O Buffer Size */ 437 #else 438 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 439 #endif 440 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ 441 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 442 /* Boot Argument Buffer Size */ 443 444 /* 445 * For booting Linux, the board info and command line data 446 * have to be in the first 64 MB of memory, since this is 447 * the maximum mapped by the Linux kernel during initialization. 448 */ 449 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 450 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 451 452 #if defined(CONFIG_CMD_KGDB) 453 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 454 #endif 455 456 /* 457 * Environment Configuration 458 */ 459 #define CONFIG_HOSTNAME "mpc8569mds" 460 #define CONFIG_ROOTPATH "/nfsroot" 461 #define CONFIG_BOOTFILE "your.uImage" 462 463 #define CONFIG_SERVERIP 192.168.1.1 464 #define CONFIG_GATEWAYIP 192.168.1.1 465 #define CONFIG_NETMASK 255.255.255.0 466 467 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ 468 469 #define CONFIG_EXTRA_ENV_SETTINGS \ 470 "netdev=eth0\0" \ 471 "consoledev=ttyS0\0" \ 472 "ramdiskaddr=600000\0" \ 473 "ramdiskfile=your.ramdisk.u-boot\0" \ 474 "fdtaddr=400000\0" \ 475 "fdtfile=your.fdt.dtb\0" \ 476 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 477 "nfsroot=$serverip:$rootpath " \ 478 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 479 "console=$consoledev,$baudrate $othbootargs\0" \ 480 "ramargs=setenv bootargs root=/dev/ram rw " \ 481 "console=$consoledev,$baudrate $othbootargs\0" \ 482 483 #define CONFIG_NFSBOOTCOMMAND \ 484 "run nfsargs;" \ 485 "tftp $loadaddr $bootfile;" \ 486 "tftp $fdtaddr $fdtfile;" \ 487 "bootm $loadaddr - $fdtaddr" 488 489 #define CONFIG_RAMBOOTCOMMAND \ 490 "run ramargs;" \ 491 "tftp $ramdiskaddr $ramdiskfile;" \ 492 "tftp $loadaddr $bootfile;" \ 493 "bootm $loadaddr $ramdiskaddr" 494 495 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 496 497 #endif /* __CONFIG_H */ 498