1if ARCH_SUNXI 2 3config SPL_LDSCRIPT 4 default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64 5 6config IDENT_STRING 7 default " Allwinner Technology" 8 9config DRAM_SUN4I 10 bool 11 help 12 Select this dram controller driver for Sun4/5/7i platforms, 13 like A10/A13/A20. 14 15config DRAM_SUN6I 16 bool 17 help 18 Select this dram controller driver for Sun6i platforms, 19 like A31/A31s. 20 21config DRAM_SUN8I_A23 22 bool 23 help 24 Select this dram controller driver for Sun8i platforms, 25 for A23 SOC. 26 27config DRAM_SUN8I_A33 28 bool 29 help 30 Select this dram controller driver for Sun8i platforms, 31 for A33 SOC. 32 33config DRAM_SUN8I_A83T 34 bool 35 help 36 Select this dram controller driver for Sun8i platforms, 37 for A83T SOC. 38 39config DRAM_SUN9I 40 bool 41 help 42 Select this dram controller driver for Sun9i platforms, 43 like A80. 44 45config DRAM_SUN50I_H6 46 bool 47 help 48 Select this dram controller driver for some sun50i platforms, 49 like H6. 50 51config SUN6I_P2WI 52 bool "Allwinner sun6i internal P2WI controller" 53 help 54 If you say yes to this option, support will be included for the 55 P2WI (Push/Pull 2 Wire Interface) controller embedded in some sunxi 56 SOCs. 57 The P2WI looks like an SMBus controller (which supports only byte 58 accesses), except that it only supports one slave device. 59 This interface is used to connect to specific PMIC devices (like the 60 AXP221). 61 62config SUN6I_PRCM 63 bool 64 help 65 Support for the PRCM (Power/Reset/Clock Management) unit available 66 in A31 SoC. 67 68config AXP_PMIC_BUS 69 bool "Sunxi AXP PMIC bus access helpers" 70 help 71 Select this PMIC bus access helpers for Sunxi platform PRCM or other 72 AXP family PMIC devices. 73 74config SUN8I_RSB 75 bool "Allwinner sunXi Reduced Serial Bus Driver" 76 help 77 Say y here to enable support for Allwinner's Reduced Serial Bus 78 (RSB) support. This controller is responsible for communicating 79 with various RSB based devices, such as AXP223, AXP8XX PMICs, 80 and AC100/AC200 ICs. 81 82config SUNXI_SRAM_ADDRESS 83 hex 84 default 0x10000 if MACH_SUN9I || MACH_SUN50I || MACH_SUN50I_H5 85 default 0x20000 if MACH_SUN50I_H6 86 default 0x0 87 ---help--- 88 Older Allwinner SoCs have their mask boot ROM mapped just below 4GB, 89 with the first SRAM region being located at address 0. 90 Some newer SoCs map the boot ROM at address 0 instead and move the 91 SRAM to a different address. 92 93config SUNXI_A64_TIMER_ERRATUM 94 bool 95 96# Note only one of these may be selected at a time! But hidden choices are 97# not supported by Kconfig 98config SUNXI_GEN_SUN4I 99 bool 100 ---help--- 101 Select this for sunxi SoCs which have resets and clocks set up 102 as the original A10 (mach-sun4i). 103 104config SUNXI_GEN_SUN6I 105 bool 106 ---help--- 107 Select this for sunxi SoCs which have sun6i like periphery, like 108 separate ahb reset control registers, custom pmic bus, new style 109 watchdog, etc. 110 111config SUNXI_DRAM_DW 112 bool 113 ---help--- 114 Select this for sunxi SoCs which uses a DRAM controller like the 115 DesignWare controller used in H3, mainly SoCs after H3, which do 116 not have official open-source DRAM initialization code, but can 117 use modified H3 DRAM initialization code. 118 119if SUNXI_DRAM_DW 120config SUNXI_DRAM_DW_16BIT 121 bool 122 ---help--- 123 Select this for sunxi SoCs with DesignWare DRAM controller and 124 have only 16-bit memory buswidth. 125 126config SUNXI_DRAM_DW_32BIT 127 bool 128 ---help--- 129 Select this for sunxi SoCs with DesignWare DRAM controller with 130 32-bit memory buswidth. 131endif 132 133config MACH_SUNXI_H3_H5 134 bool 135 select DM_I2C 136 select PHY_SUN4I_USB 137 select SUNXI_DE2 138 select SUNXI_DRAM_DW 139 select SUNXI_DRAM_DW_32BIT 140 select SUNXI_GEN_SUN6I 141 select SUPPORT_SPL 142 143# TODO: try out A80's 8GiB DRAM space 144config SUNXI_DRAM_MAX_SIZE 145 hex 146 default 0xC0000000 if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN50I_H6 147 default 0x80000000 148 149choice 150 prompt "Sunxi SoC Variant" 151 optional 152 153config MACH_SUN4I 154 bool "sun4i (Allwinner A10)" 155 select CPU_V7A 156 select ARM_CORTEX_CPU_IS_UP 157 select PHY_SUN4I_USB 158 select DRAM_SUN4I 159 select SUNXI_GEN_SUN4I 160 select SUPPORT_SPL 161 162config MACH_SUN5I 163 bool "sun5i (Allwinner A13)" 164 select CPU_V7A 165 select ARM_CORTEX_CPU_IS_UP 166 select DRAM_SUN4I 167 select PHY_SUN4I_USB 168 select SUNXI_GEN_SUN4I 169 select SUPPORT_SPL 170 imply CONS_INDEX_2 if !DM_SERIAL 171 172config MACH_SUN6I 173 bool "sun6i (Allwinner A31)" 174 select CPU_V7A 175 select CPU_V7_HAS_NONSEC 176 select CPU_V7_HAS_VIRT 177 select ARCH_SUPPORT_PSCI 178 select DRAM_SUN6I 179 select PHY_SUN4I_USB 180 select SUN6I_P2WI 181 select SUN6I_PRCM 182 select SUNXI_GEN_SUN6I 183 select SUPPORT_SPL 184 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT 185 186config MACH_SUN7I 187 bool "sun7i (Allwinner A20)" 188 select CPU_V7A 189 select CPU_V7_HAS_NONSEC 190 select CPU_V7_HAS_VIRT 191 select ARCH_SUPPORT_PSCI 192 select DRAM_SUN4I 193 select PHY_SUN4I_USB 194 select SUNXI_GEN_SUN4I 195 select SUPPORT_SPL 196 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT 197 198config MACH_SUN8I_A23 199 bool "sun8i (Allwinner A23)" 200 select CPU_V7A 201 select CPU_V7_HAS_NONSEC 202 select CPU_V7_HAS_VIRT 203 select ARCH_SUPPORT_PSCI 204 select DRAM_SUN8I_A23 205 select PHY_SUN4I_USB 206 select SUNXI_GEN_SUN6I 207 select SUPPORT_SPL 208 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT 209 imply CONS_INDEX_5 if !DM_SERIAL 210 211config MACH_SUN8I_A33 212 bool "sun8i (Allwinner A33)" 213 select CPU_V7A 214 select CPU_V7_HAS_NONSEC 215 select CPU_V7_HAS_VIRT 216 select ARCH_SUPPORT_PSCI 217 select DRAM_SUN8I_A33 218 select PHY_SUN4I_USB 219 select SUNXI_GEN_SUN6I 220 select SUPPORT_SPL 221 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT 222 imply CONS_INDEX_5 if !DM_SERIAL 223 224config MACH_SUN8I_A83T 225 bool "sun8i (Allwinner A83T)" 226 select CPU_V7A 227 select DRAM_SUN8I_A83T 228 select PHY_SUN4I_USB 229 select SUNXI_GEN_SUN6I 230 select MMC_SUNXI_HAS_NEW_MODE 231 select MMC_SUNXI_HAS_MODE_SWITCH 232 select SUPPORT_SPL 233 234config MACH_SUN8I_H3 235 bool "sun8i (Allwinner H3)" 236 select CPU_V7A 237 select CPU_V7_HAS_NONSEC 238 select CPU_V7_HAS_VIRT 239 select ARCH_SUPPORT_PSCI 240 select MACH_SUNXI_H3_H5 241 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT 242 243config MACH_SUN8I_R40 244 bool "sun8i (Allwinner R40)" 245 select CPU_V7A 246 select CPU_V7_HAS_NONSEC 247 select CPU_V7_HAS_VIRT 248 select ARCH_SUPPORT_PSCI 249 select SUNXI_GEN_SUN6I 250 select SUPPORT_SPL 251 select SUNXI_DRAM_DW 252 select SUNXI_DRAM_DW_32BIT 253 254config MACH_SUN8I_V3S 255 bool "sun8i (Allwinner V3s)" 256 select CPU_V7A 257 select CPU_V7_HAS_NONSEC 258 select CPU_V7_HAS_VIRT 259 select ARCH_SUPPORT_PSCI 260 select SUNXI_GEN_SUN6I 261 select SUNXI_DRAM_DW 262 select SUNXI_DRAM_DW_16BIT 263 select SUPPORT_SPL 264 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT 265 266config MACH_SUN9I 267 bool "sun9i (Allwinner A80)" 268 select CPU_V7A 269 select DRAM_SUN9I 270 select SUN6I_PRCM 271 select SUNXI_GEN_SUN6I 272 select SUN8I_RSB 273 select SUPPORT_SPL 274 275config MACH_SUN50I 276 bool "sun50i (Allwinner A64)" 277 select ARM64 278 select SPI 279 select DM_I2C 280 select DM_SPI if SPI 281 select DM_SPI_FLASH 282 select PHY_SUN4I_USB 283 select SUN6I_PRCM 284 select SUNXI_DE2 285 select SUNXI_GEN_SUN6I 286 select MMC_SUNXI_HAS_NEW_MODE 287 select SUPPORT_SPL 288 select SUNXI_DRAM_DW 289 select SUNXI_DRAM_DW_32BIT 290 select FIT 291 select SPL_LOAD_FIT 292 select SUNXI_A64_TIMER_ERRATUM 293 294config MACH_SUN50I_H5 295 bool "sun50i (Allwinner H5)" 296 select ARM64 297 select MACH_SUNXI_H3_H5 298 select FIT 299 select SPL_LOAD_FIT 300 301config MACH_SUN50I_H6 302 bool "sun50i (Allwinner H6)" 303 select ARM64 304 select SUPPORT_SPL 305 select FIT 306 select PHY_SUN4I_USB 307 select SPL_LOAD_FIT 308 select DRAM_SUN50I_H6 309 310endchoice 311 312# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33" 313config MACH_SUN8I 314 bool 315 select SUN8I_RSB 316 select SUN6I_PRCM 317 default y if MACH_SUN8I_A23 318 default y if MACH_SUN8I_A33 319 default y if MACH_SUN8I_A83T 320 default y if MACH_SUNXI_H3_H5 321 default y if MACH_SUN8I_R40 322 default y if MACH_SUN8I_V3S 323 324config RESERVE_ALLWINNER_BOOT0_HEADER 325 bool "reserve space for Allwinner boot0 header" 326 select ENABLE_ARM_SOC_BOOT0_HOOK 327 ---help--- 328 Prepend a 1536 byte (empty) header to the U-Boot image file, to be 329 filled with magic values post build. The Allwinner provided boot0 330 blob relies on this information to load and execute U-Boot. 331 Only needed on 64-bit Allwinner boards so far when using boot0. 332 333config ARM_BOOT_HOOK_RMR 334 bool 335 depends on ARM64 336 default y 337 select ENABLE_ARM_SOC_BOOT0_HOOK 338 ---help--- 339 Insert some ARM32 code at the very beginning of the U-Boot binary 340 which uses an RMR register write to bring the core into AArch64 mode. 341 The very first instruction acts as a switch, since it's carefully 342 chosen to be a NOP in one mode and a branch in the other, so the 343 code would only be executed if not already in AArch64. 344 This allows both the SPL and the U-Boot proper to be entered in 345 either mode and switch to AArch64 if needed. 346 347if SUNXI_DRAM_DW || DRAM_SUN50I_H6 348config SUNXI_DRAM_DDR3 349 bool 350 351config SUNXI_DRAM_DDR2 352 bool 353 354config SUNXI_DRAM_LPDDR3 355 bool 356 357choice 358 prompt "DRAM Type and Timing" 359 default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S 360 default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S 361 362config SUNXI_DRAM_DDR3_1333 363 bool "DDR3 1333" 364 select SUNXI_DRAM_DDR3 365 depends on !MACH_SUN8I_V3S 366 ---help--- 367 This option is the original only supported memory type, which suits 368 many H3/H5/A64 boards available now. 369 370config SUNXI_DRAM_LPDDR3_STOCK 371 bool "LPDDR3 with Allwinner stock configuration" 372 select SUNXI_DRAM_LPDDR3 373 ---help--- 374 This option is the LPDDR3 timing used by the stock boot0 by 375 Allwinner. 376 377config SUNXI_DRAM_H6_LPDDR3 378 bool "LPDDR3 DRAM chips on the H6 DRAM controller" 379 select SUNXI_DRAM_LPDDR3 380 depends on DRAM_SUN50I_H6 381 ---help--- 382 This option is the LPDDR3 timing used by the stock boot0 by 383 Allwinner. 384 385config SUNXI_DRAM_H6_DDR3_1333 386 bool "DDR3-1333 boot0 timings on the H6 DRAM controller" 387 select SUNXI_DRAM_DDR3 388 depends on DRAM_SUN50I_H6 389 ---help--- 390 This option is the DDR3 timing used by the boot0 on H6 TV boxes 391 which use a DDR3-1333 timing. 392 393config SUNXI_DRAM_DDR2_V3S 394 bool "DDR2 found in V3s chip" 395 select SUNXI_DRAM_DDR2 396 depends on MACH_SUN8I_V3S 397 ---help--- 398 This option is only for the DDR2 memory chip which is co-packaged in 399 Allwinner V3s SoC. 400 401endchoice 402endif 403 404config DRAM_TYPE 405 int "sunxi dram type" 406 depends on MACH_SUN8I_A83T 407 default 3 408 ---help--- 409 Set the dram type, 3: DDR3, 7: LPDDR3 410 411config DRAM_CLK 412 int "sunxi dram clock speed" 413 default 792 if MACH_SUN9I 414 default 648 if MACH_SUN8I_R40 415 default 312 if MACH_SUN6I || MACH_SUN8I 416 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \ 417 MACH_SUN8I_V3S 418 default 672 if MACH_SUN50I 419 default 744 if MACH_SUN50I_H6 420 ---help--- 421 Set the dram clock speed, valid range 240 - 480 (prior to sun9i), 422 must be a multiple of 24. For the sun9i (A80), the tested values 423 (for DDR3-1600) are 312 to 792. 424 425if MACH_SUN5I || MACH_SUN7I 426config DRAM_MBUS_CLK 427 int "sunxi mbus clock speed" 428 default 300 429 ---help--- 430 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz. 431 432endif 433 434config DRAM_ZQ 435 int "sunxi dram zq value" 436 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || \ 437 MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_A83T 438 default 127 if MACH_SUN7I 439 default 14779 if MACH_SUN8I_V3S 440 default 3881979 if MACH_SUNXI_H3_H5 || MACH_SUN8I_R40 || MACH_SUN50I_H6 441 default 4145117 if MACH_SUN9I 442 default 3881915 if MACH_SUN50I 443 ---help--- 444 Set the dram zq value. 445 446config DRAM_ODT_EN 447 bool "sunxi dram odt enable" 448 default y if MACH_SUN8I_A23 449 default y if MACH_SUNXI_H3_H5 450 default y if MACH_SUN8I_R40 451 default y if MACH_SUN50I 452 default y if MACH_SUN50I_H6 453 ---help--- 454 Select this to enable dram odt (on die termination). 455 456if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I 457config DRAM_EMR1 458 int "sunxi dram emr1 value" 459 default 0 if MACH_SUN4I 460 default 4 if MACH_SUN5I || MACH_SUN7I 461 ---help--- 462 Set the dram controller emr1 value. 463 464config DRAM_TPR3 465 hex "sunxi dram tpr3 value" 466 default 0 467 ---help--- 468 Set the dram controller tpr3 parameter. This parameter configures 469 the delay on the command lane and also phase shifts, which are 470 applied for sampling incoming read data. The default value 0 471 means that no phase/delay adjustments are necessary. Properly 472 configuring this parameter increases reliability at high DRAM 473 clock speeds. 474 475config DRAM_DQS_GATING_DELAY 476 hex "sunxi dram dqs_gating_delay value" 477 default 0 478 ---help--- 479 Set the dram controller dqs_gating_delay parmeter. Each byte 480 encodes the DQS gating delay for each byte lane. The delay 481 granularity is 1/4 cycle. For example, the value 0x05060606 482 means that the delay is 5 quarter-cycles for one lane (1.25 483 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes. 484 The default value 0 means autodetection. The results of hardware 485 autodetection are not very reliable and depend on the chip 486 temperature (sometimes producing different results on cold start 487 and warm reboot). But the accuracy of hardware autodetection 488 is usually good enough, unless running at really high DRAM 489 clocks speeds (up to 600MHz). If unsure, keep as 0. 490 491choice 492 prompt "sunxi dram timings" 493 default DRAM_TIMINGS_VENDOR_MAGIC 494 ---help--- 495 Select the timings of the DDR3 chips. 496 497config DRAM_TIMINGS_VENDOR_MAGIC 498 bool "Magic vendor timings from Android" 499 ---help--- 500 The same DRAM timings as in the Allwinner boot0 bootloader. 501 502config DRAM_TIMINGS_DDR3_1066F_1333H 503 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F" 504 ---help--- 505 Use the timings of the standard JEDEC DDR3-1066F speed bin for 506 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin 507 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips 508 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333 509 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm 510 that down binning to DDR3-1066F is supported (because DDR3-1066F 511 uses a bit faster timings than DDR3-1333H). 512 513config DRAM_TIMINGS_DDR3_800E_1066G_1333J 514 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J" 515 ---help--- 516 Use the timings of the slowest possible JEDEC speed bin for the 517 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be 518 DDR3-800E, DDR3-1066G or DDR3-1333J. 519 520endchoice 521 522endif 523 524if MACH_SUN8I_A23 525config DRAM_ODT_CORRECTION 526 int "sunxi dram odt correction value" 527 default 0 528 ---help--- 529 Set the dram odt correction value (range -255 - 255). In allwinner 530 fex files, this option is found in bits 8-15 of the u32 odt_en variable 531 in the [dram] section. When bit 31 of the odt_en variable is set 532 then the correction is negative. Usually the value for this is 0. 533endif 534 535config SYS_CLK_FREQ 536 default 1008000000 if MACH_SUN4I 537 default 1008000000 if MACH_SUN5I 538 default 1008000000 if MACH_SUN6I 539 default 912000000 if MACH_SUN7I 540 default 816000000 if MACH_SUN50I || MACH_SUN50I_H5 541 default 1008000000 if MACH_SUN8I 542 default 1008000000 if MACH_SUN9I 543 default 888000000 if MACH_SUN50I_H6 544 545config SYS_CONFIG_NAME 546 default "sun4i" if MACH_SUN4I 547 default "sun5i" if MACH_SUN5I 548 default "sun6i" if MACH_SUN6I 549 default "sun7i" if MACH_SUN7I 550 default "sun8i" if MACH_SUN8I 551 default "sun9i" if MACH_SUN9I 552 default "sun50i" if MACH_SUN50I 553 default "sun50i" if MACH_SUN50I_H6 554 555config SYS_BOARD 556 default "sunxi" 557 558config SYS_SOC 559 default "sunxi" 560 561config UART0_PORT_F 562 bool "UART0 on MicroSD breakout board" 563 default n 564 ---help--- 565 Repurpose the SD card slot for getting access to the UART0 serial 566 console. Primarily useful only for low level u-boot debugging on 567 tablets, where normal UART0 is difficult to access and requires 568 device disassembly and/or soldering. As the SD card can't be used 569 at the same time, the system can be only booted in the FEL mode. 570 Only enable this if you really know what you are doing. 571 572config OLD_SUNXI_KERNEL_COMPAT 573 bool "Enable workarounds for booting old kernels" 574 default n 575 ---help--- 576 Set this to enable various workarounds for old kernels, this results in 577 sub-optimal settings for newer kernels, only enable if needed. 578 579config MACPWR 580 string "MAC power pin" 581 default "" 582 help 583 Set the pin used to power the MAC. This takes a string in the format 584 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. 585 586config MMC0_CD_PIN 587 string "Card detect pin for mmc0" 588 default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I 589 default "" 590 ---help--- 591 Set the card detect pin for mmc0, leave empty to not use cd. This 592 takes a string in the format understood by sunxi_name_to_gpio, e.g. 593 PH1 for pin 1 of port H. 594 595config MMC1_CD_PIN 596 string "Card detect pin for mmc1" 597 default "" 598 ---help--- 599 See MMC0_CD_PIN help text. 600 601config MMC2_CD_PIN 602 string "Card detect pin for mmc2" 603 default "" 604 ---help--- 605 See MMC0_CD_PIN help text. 606 607config MMC3_CD_PIN 608 string "Card detect pin for mmc3" 609 default "" 610 ---help--- 611 See MMC0_CD_PIN help text. 612 613config MMC1_PINS 614 string "Pins for mmc1" 615 default "" 616 ---help--- 617 Set the pins used for mmc1, when applicable. This takes a string in the 618 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H. 619 620config MMC2_PINS 621 string "Pins for mmc2" 622 default "" 623 ---help--- 624 See MMC1_PINS help text. 625 626config MMC3_PINS 627 string "Pins for mmc3" 628 default "" 629 ---help--- 630 See MMC1_PINS help text. 631 632config MMC_SUNXI_SLOT_EXTRA 633 int "mmc extra slot number" 634 default -1 635 ---help--- 636 sunxi builds always enable mmc0, some boards also have a second sdcard 637 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable 638 support for this. 639 640config INITIAL_USB_SCAN_DELAY 641 int "delay initial usb scan by x ms to allow builtin devices to init" 642 default 0 643 ---help--- 644 Some boards have on board usb devices which need longer than the 645 USB spec's 1 second to connect from board powerup. Set this config 646 option to a non 0 value to add an extra delay before the first usb 647 bus scan. 648 649config USB0_VBUS_PIN 650 string "Vbus enable pin for usb0 (otg)" 651 default "" 652 ---help--- 653 Set the Vbus enable pin for usb0 (otg). This takes a string in the 654 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. 655 656config USB0_VBUS_DET 657 string "Vbus detect pin for usb0 (otg)" 658 default "" 659 ---help--- 660 Set the Vbus detect pin for usb0 (otg). This takes a string in the 661 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. 662 663config USB0_ID_DET 664 string "ID detect pin for usb0 (otg)" 665 default "" 666 ---help--- 667 Set the ID detect pin for usb0 (otg). This takes a string in the 668 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. 669 670config USB1_VBUS_PIN 671 string "Vbus enable pin for usb1 (ehci0)" 672 default "PH6" if MACH_SUN4I || MACH_SUN7I 673 default "PH27" if MACH_SUN6I 674 ---help--- 675 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes 676 a string in the format understood by sunxi_name_to_gpio, e.g. 677 PH1 for pin 1 of port H. 678 679config USB2_VBUS_PIN 680 string "Vbus enable pin for usb2 (ehci1)" 681 default "PH3" if MACH_SUN4I || MACH_SUN7I 682 default "PH24" if MACH_SUN6I 683 ---help--- 684 See USB1_VBUS_PIN help text. 685 686config USB3_VBUS_PIN 687 string "Vbus enable pin for usb3 (ehci2)" 688 default "" 689 ---help--- 690 See USB1_VBUS_PIN help text. 691 692config I2C0_ENABLE 693 bool "Enable I2C/TWI controller 0" 694 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40 695 default n if MACH_SUN6I || MACH_SUN8I 696 select CMD_I2C 697 ---help--- 698 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling 699 its clock and setting up the bus. This is especially useful on devices 700 with slaves connected to the bus or with pins exposed through e.g. an 701 expansion port/header. 702 703config I2C1_ENABLE 704 bool "Enable I2C/TWI controller 1" 705 default n 706 select CMD_I2C 707 ---help--- 708 See I2C0_ENABLE help text. 709 710config I2C2_ENABLE 711 bool "Enable I2C/TWI controller 2" 712 default n 713 select CMD_I2C 714 ---help--- 715 See I2C0_ENABLE help text. 716 717if MACH_SUN6I || MACH_SUN7I 718config I2C3_ENABLE 719 bool "Enable I2C/TWI controller 3" 720 default n 721 select CMD_I2C 722 ---help--- 723 See I2C0_ENABLE help text. 724endif 725 726if SUNXI_GEN_SUN6I 727config R_I2C_ENABLE 728 bool "Enable the PRCM I2C/TWI controller" 729 # This is used for the pmic on H3 730 default y if SY8106A_POWER 731 select CMD_I2C 732 ---help--- 733 Set this to y to enable the I2C controller which is part of the PRCM. 734endif 735 736if MACH_SUN7I 737config I2C4_ENABLE 738 bool "Enable I2C/TWI controller 4" 739 default n 740 select CMD_I2C 741 ---help--- 742 See I2C0_ENABLE help text. 743endif 744 745config AXP_GPIO 746 bool "Enable support for gpio-s on axp PMICs" 747 default n 748 ---help--- 749 Say Y here to enable support for the gpio pins of the axp PMIC ICs. 750 751config VIDEO_SUNXI 752 bool "Enable graphical uboot console on HDMI, LCD or VGA" 753 depends on !MACH_SUN8I_A83T 754 depends on !MACH_SUNXI_H3_H5 755 depends on !MACH_SUN8I_R40 756 depends on !MACH_SUN8I_V3S 757 depends on !MACH_SUN9I 758 depends on !MACH_SUN50I 759 depends on !MACH_SUN50I_H6 760 select VIDEO 761 imply VIDEO_DT_SIMPLEFB 762 default y 763 ---help--- 764 Say Y here to add support for using a cfb console on the HDMI, LCD 765 or VGA output found on most sunxi devices. See doc/README.video for 766 info on how to select the video output and mode. 767 768config VIDEO_HDMI 769 bool "HDMI output support" 770 depends on VIDEO_SUNXI && !MACH_SUN8I 771 default y 772 ---help--- 773 Say Y here to add support for outputting video over HDMI. 774 775config VIDEO_VGA 776 bool "VGA output support" 777 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN7I) 778 default n 779 ---help--- 780 Say Y here to add support for outputting video over VGA. 781 782config VIDEO_VGA_VIA_LCD 783 bool "VGA via LCD controller support" 784 depends on VIDEO_SUNXI && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I) 785 default n 786 ---help--- 787 Say Y here to add support for external DACs connected to the parallel 788 LCD interface driving a VGA connector, such as found on the 789 Olimex A13 boards. 790 791config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH 792 bool "Force sync active high for VGA via LCD controller support" 793 depends on VIDEO_VGA_VIA_LCD 794 default n 795 ---help--- 796 Say Y here if you've a board which uses opendrain drivers for the vga 797 hsync and vsync signals. Opendrain drivers cannot generate steep enough 798 positive edges for a stable video output, so on boards with opendrain 799 drivers the sync signals must always be active high. 800 801config VIDEO_VGA_EXTERNAL_DAC_EN 802 string "LCD panel power enable pin" 803 depends on VIDEO_VGA_VIA_LCD 804 default "" 805 ---help--- 806 Set the enable pin for the external VGA DAC. This takes a string in the 807 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. 808 809config VIDEO_COMPOSITE 810 bool "Composite video output support" 811 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I) 812 default n 813 ---help--- 814 Say Y here to add support for outputting composite video. 815 816config VIDEO_LCD_MODE 817 string "LCD panel timing details" 818 depends on VIDEO_SUNXI 819 default "" 820 ---help--- 821 LCD panel timing details string, leave empty if there is no LCD panel. 822 This is in drivers/video/videomodes.c: video_get_params() format, e.g. 823 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0 824 Also see: http://linux-sunxi.org/LCD 825 826config VIDEO_LCD_DCLK_PHASE 827 int "LCD panel display clock phase" 828 depends on VIDEO_SUNXI || DM_VIDEO 829 default 1 830 ---help--- 831 Select LCD panel display clock phase shift, range 0-3. 832 833config VIDEO_LCD_POWER 834 string "LCD panel power enable pin" 835 depends on VIDEO_SUNXI 836 default "" 837 ---help--- 838 Set the power enable pin for the LCD panel. This takes a string in the 839 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. 840 841config VIDEO_LCD_RESET 842 string "LCD panel reset pin" 843 depends on VIDEO_SUNXI 844 default "" 845 ---help--- 846 Set the reset pin for the LCD panel. This takes a string in the format 847 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. 848 849config VIDEO_LCD_BL_EN 850 string "LCD panel backlight enable pin" 851 depends on VIDEO_SUNXI 852 default "" 853 ---help--- 854 Set the backlight enable pin for the LCD panel. This takes a string in the 855 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of 856 port H. 857 858config VIDEO_LCD_BL_PWM 859 string "LCD panel backlight pwm pin" 860 depends on VIDEO_SUNXI 861 default "" 862 ---help--- 863 Set the backlight pwm pin for the LCD panel. This takes a string in the 864 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. 865 866config VIDEO_LCD_BL_PWM_ACTIVE_LOW 867 bool "LCD panel backlight pwm is inverted" 868 depends on VIDEO_SUNXI 869 default y 870 ---help--- 871 Set this if the backlight pwm output is active low. 872 873config VIDEO_LCD_PANEL_I2C 874 bool "LCD panel needs to be configured via i2c" 875 depends on VIDEO_SUNXI 876 default n 877 select CMD_I2C 878 ---help--- 879 Say y here if the LCD panel needs to be configured via i2c. This 880 will add a bitbang i2c controller using gpios to talk to the LCD. 881 882config VIDEO_LCD_PANEL_I2C_SDA 883 string "LCD panel i2c interface SDA pin" 884 depends on VIDEO_LCD_PANEL_I2C 885 default "PG12" 886 ---help--- 887 Set the SDA pin for the LCD i2c interface. This takes a string in the 888 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. 889 890config VIDEO_LCD_PANEL_I2C_SCL 891 string "LCD panel i2c interface SCL pin" 892 depends on VIDEO_LCD_PANEL_I2C 893 default "PG10" 894 ---help--- 895 Set the SCL pin for the LCD i2c interface. This takes a string in the 896 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. 897 898 899# Note only one of these may be selected at a time! But hidden choices are 900# not supported by Kconfig 901config VIDEO_LCD_IF_PARALLEL 902 bool 903 904config VIDEO_LCD_IF_LVDS 905 bool 906 907config SUNXI_DE2 908 bool 909 default n 910 911config VIDEO_DE2 912 bool "Display Engine 2 video driver" 913 depends on SUNXI_DE2 914 select DM_VIDEO 915 select DISPLAY 916 imply VIDEO_DT_SIMPLEFB 917 default y 918 ---help--- 919 Say y here if you want to build DE2 video driver which is present on 920 newer SoCs. Currently only HDMI output is supported. 921 922 923choice 924 prompt "LCD panel support" 925 depends on VIDEO_SUNXI 926 ---help--- 927 Select which type of LCD panel to support. 928 929config VIDEO_LCD_PANEL_PARALLEL 930 bool "Generic parallel interface LCD panel" 931 select VIDEO_LCD_IF_PARALLEL 932 933config VIDEO_LCD_PANEL_LVDS 934 bool "Generic lvds interface LCD panel" 935 select VIDEO_LCD_IF_LVDS 936 937config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828 938 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip" 939 select VIDEO_LCD_SSD2828 940 select VIDEO_LCD_IF_PARALLEL 941 ---help--- 942 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0 943 944config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804 945 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip" 946 select VIDEO_LCD_ANX9804 947 select VIDEO_LCD_IF_PARALLEL 948 select VIDEO_LCD_PANEL_I2C 949 ---help--- 950 Select this for eDP LCD panels with 4 lanes running at 1.62G, 951 connected via an ANX9804 bridge chip. 952 953config VIDEO_LCD_PANEL_HITACHI_TX18D42VM 954 bool "Hitachi tx18d42vm LCD panel" 955 select VIDEO_LCD_HITACHI_TX18D42VM 956 select VIDEO_LCD_IF_LVDS 957 ---help--- 958 7.85" 1024x768 Hitachi tx18d42vm LCD panel support 959 960config VIDEO_LCD_TL059WV5C0 961 bool "tl059wv5c0 LCD panel" 962 select VIDEO_LCD_PANEL_I2C 963 select VIDEO_LCD_IF_PARALLEL 964 ---help--- 965 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and 966 Aigo M60/M608/M606 tablets. 967 968endchoice 969 970config SATAPWR 971 string "SATA power pin" 972 default "" 973 help 974 Set the pins used to power the SATA. This takes a string in the 975 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of 976 port H. 977 978config GMAC_TX_DELAY 979 int "GMAC Transmit Clock Delay Chain" 980 default 0 981 ---help--- 982 Set the GMAC Transmit Clock Delay Chain value. 983 984config SPL_STACK_R_ADDR 985 default 0x4fe00000 if MACH_SUN4I 986 default 0x4fe00000 if MACH_SUN5I 987 default 0x4fe00000 if MACH_SUN6I 988 default 0x4fe00000 if MACH_SUN7I 989 default 0x4fe00000 if MACH_SUN8I 990 default 0x2fe00000 if MACH_SUN9I 991 default 0x4fe00000 if MACH_SUN50I 992 default 0x4fe00000 if MACH_SUN50I_H6 993 994config SPL_SPI_SUNXI 995 bool "Support for SPI Flash on Allwinner SoCs in SPL" 996 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I 997 help 998 Enable support for SPI Flash. This option allows SPL to read from 999 sunxi SPI Flash. It uses the same method as the boot ROM, so does 1000 not need any extra configuration. 1001 1002config PINE64_DT_SELECTION 1003 bool "Enable Pine64 device tree selection code" 1004 depends on MACH_SUN50I 1005 help 1006 The original Pine A64 and Pine A64+ are similar but different 1007 boards and can be differed by the DRAM size. Pine A64 has 1008 512MiB DRAM, and Pine A64+ has 1GiB or 2GiB. By selecting this 1009 option, the device tree selection code specific to Pine64 which 1010 utilizes the DRAM size will be enabled. 1011 1012endif 1013