1 /* 2 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CONTEXT_H 8 #define CONTEXT_H 9 10 #include <lib/utils_def.h> 11 12 /******************************************************************************* 13 * Constants that allow assembler code to access members of and the 'gp_regs' 14 * structure at their correct offsets. 15 ******************************************************************************/ 16 #define CTX_GPREGS_OFFSET U(0x0) 17 #define CTX_GPREG_X0 U(0x0) 18 #define CTX_GPREG_X1 U(0x8) 19 #define CTX_GPREG_X2 U(0x10) 20 #define CTX_GPREG_X3 U(0x18) 21 #define CTX_GPREG_X4 U(0x20) 22 #define CTX_GPREG_X5 U(0x28) 23 #define CTX_GPREG_X6 U(0x30) 24 #define CTX_GPREG_X7 U(0x38) 25 #define CTX_GPREG_X8 U(0x40) 26 #define CTX_GPREG_X9 U(0x48) 27 #define CTX_GPREG_X10 U(0x50) 28 #define CTX_GPREG_X11 U(0x58) 29 #define CTX_GPREG_X12 U(0x60) 30 #define CTX_GPREG_X13 U(0x68) 31 #define CTX_GPREG_X14 U(0x70) 32 #define CTX_GPREG_X15 U(0x78) 33 #define CTX_GPREG_X16 U(0x80) 34 #define CTX_GPREG_X17 U(0x88) 35 #define CTX_GPREG_X18 U(0x90) 36 #define CTX_GPREG_X19 U(0x98) 37 #define CTX_GPREG_X20 U(0xa0) 38 #define CTX_GPREG_X21 U(0xa8) 39 #define CTX_GPREG_X22 U(0xb0) 40 #define CTX_GPREG_X23 U(0xb8) 41 #define CTX_GPREG_X24 U(0xc0) 42 #define CTX_GPREG_X25 U(0xc8) 43 #define CTX_GPREG_X26 U(0xd0) 44 #define CTX_GPREG_X27 U(0xd8) 45 #define CTX_GPREG_X28 U(0xe0) 46 #define CTX_GPREG_X29 U(0xe8) 47 #define CTX_GPREG_LR U(0xf0) 48 #define CTX_GPREG_SP_EL0 U(0xf8) 49 #define CTX_GPREGS_END U(0x100) 50 51 /******************************************************************************* 52 * Constants that allow assembler code to access members of and the 'el3_state' 53 * structure at their correct offsets. Note that some of the registers are only 54 * 32-bits wide but are stored as 64-bit values for convenience 55 ******************************************************************************/ 56 #define CTX_EL3STATE_OFFSET (CTX_GPREGS_OFFSET + CTX_GPREGS_END) 57 #define CTX_SCR_EL3 U(0x0) 58 #define CTX_ESR_EL3 U(0x8) 59 #define CTX_RUNTIME_SP U(0x10) 60 #define CTX_SPSR_EL3 U(0x18) 61 #define CTX_ELR_EL3 U(0x20) 62 #define CTX_PMCR_EL0 U(0x28) 63 #define CTX_EL3STATE_END U(0x30) 64 65 /******************************************************************************* 66 * Constants that allow assembler code to access members of and the 67 * 'el1_sys_regs' structure at their correct offsets. Note that some of the 68 * registers are only 32-bits wide but are stored as 64-bit values for 69 * convenience 70 ******************************************************************************/ 71 #define CTX_SYSREGS_OFFSET (CTX_EL3STATE_OFFSET + CTX_EL3STATE_END) 72 #define CTX_SPSR_EL1 U(0x0) 73 #define CTX_ELR_EL1 U(0x8) 74 #define CTX_SCTLR_EL1 U(0x10) 75 #define CTX_ACTLR_EL1 U(0x18) 76 #define CTX_CPACR_EL1 U(0x20) 77 #define CTX_CSSELR_EL1 U(0x28) 78 #define CTX_SP_EL1 U(0x30) 79 #define CTX_ESR_EL1 U(0x38) 80 #define CTX_TTBR0_EL1 U(0x40) 81 #define CTX_TTBR1_EL1 U(0x48) 82 #define CTX_MAIR_EL1 U(0x50) 83 #define CTX_AMAIR_EL1 U(0x58) 84 #define CTX_TCR_EL1 U(0x60) 85 #define CTX_TPIDR_EL1 U(0x68) 86 #define CTX_TPIDR_EL0 U(0x70) 87 #define CTX_TPIDRRO_EL0 U(0x78) 88 #define CTX_PAR_EL1 U(0x80) 89 #define CTX_FAR_EL1 U(0x88) 90 #define CTX_AFSR0_EL1 U(0x90) 91 #define CTX_AFSR1_EL1 U(0x98) 92 #define CTX_CONTEXTIDR_EL1 U(0xa0) 93 #define CTX_VBAR_EL1 U(0xa8) 94 95 /* 96 * If the platform is AArch64-only, there is no need to save and restore these 97 * AArch32 registers. 98 */ 99 #if CTX_INCLUDE_AARCH32_REGS 100 #define CTX_SPSR_ABT U(0xb0) /* Align to the next 16 byte boundary */ 101 #define CTX_SPSR_UND U(0xb8) 102 #define CTX_SPSR_IRQ U(0xc0) 103 #define CTX_SPSR_FIQ U(0xc8) 104 #define CTX_DACR32_EL2 U(0xd0) 105 #define CTX_IFSR32_EL2 U(0xd8) 106 #define CTX_AARCH32_END U(0xe0) /* Align to the next 16 byte boundary */ 107 #else 108 #define CTX_AARCH32_END U(0xb0) /* Align to the next 16 byte boundary */ 109 #endif /* CTX_INCLUDE_AARCH32_REGS */ 110 111 /* 112 * If the timer registers aren't saved and restored, we don't have to reserve 113 * space for them in the context 114 */ 115 #if NS_TIMER_SWITCH 116 #define CTX_CNTP_CTL_EL0 (CTX_AARCH32_END + U(0x0)) 117 #define CTX_CNTP_CVAL_EL0 (CTX_AARCH32_END + U(0x8)) 118 #define CTX_CNTV_CTL_EL0 (CTX_AARCH32_END + U(0x10)) 119 #define CTX_CNTV_CVAL_EL0 (CTX_AARCH32_END + U(0x18)) 120 #define CTX_CNTKCTL_EL1 (CTX_AARCH32_END + U(0x20)) 121 #define CTX_TIMER_SYSREGS_END (CTX_AARCH32_END + U(0x30)) /* Align to the next 16 byte boundary */ 122 #else 123 #define CTX_TIMER_SYSREGS_END CTX_AARCH32_END 124 #endif /* NS_TIMER_SWITCH */ 125 126 #if CTX_INCLUDE_MTE_REGS 127 #define CTX_TFSRE0_EL1 (CTX_TIMER_SYSREGS_END + U(0x0)) 128 #define CTX_TFSR_EL1 (CTX_TIMER_SYSREGS_END + U(0x8)) 129 #define CTX_RGSR_EL1 (CTX_TIMER_SYSREGS_END + U(0x10)) 130 #define CTX_GCR_EL1 (CTX_TIMER_SYSREGS_END + U(0x18)) 131 132 /* Align to the next 16 byte boundary */ 133 #define CTX_MTE_REGS_END (CTX_TIMER_SYSREGS_END + U(0x20)) 134 #else 135 #define CTX_MTE_REGS_END CTX_TIMER_SYSREGS_END 136 #endif /* CTX_INCLUDE_MTE_REGS */ 137 138 /* 139 * End of system registers. 140 */ 141 #define CTX_SYSREGS_END CTX_MTE_REGS_END 142 143 /******************************************************************************* 144 * Constants that allow assembler code to access members of and the 'fp_regs' 145 * structure at their correct offsets. 146 ******************************************************************************/ 147 #define CTX_FPREGS_OFFSET (CTX_SYSREGS_OFFSET + CTX_SYSREGS_END) 148 #if CTX_INCLUDE_FPREGS 149 #define CTX_FP_Q0 U(0x0) 150 #define CTX_FP_Q1 U(0x10) 151 #define CTX_FP_Q2 U(0x20) 152 #define CTX_FP_Q3 U(0x30) 153 #define CTX_FP_Q4 U(0x40) 154 #define CTX_FP_Q5 U(0x50) 155 #define CTX_FP_Q6 U(0x60) 156 #define CTX_FP_Q7 U(0x70) 157 #define CTX_FP_Q8 U(0x80) 158 #define CTX_FP_Q9 U(0x90) 159 #define CTX_FP_Q10 U(0xa0) 160 #define CTX_FP_Q11 U(0xb0) 161 #define CTX_FP_Q12 U(0xc0) 162 #define CTX_FP_Q13 U(0xd0) 163 #define CTX_FP_Q14 U(0xe0) 164 #define CTX_FP_Q15 U(0xf0) 165 #define CTX_FP_Q16 U(0x100) 166 #define CTX_FP_Q17 U(0x110) 167 #define CTX_FP_Q18 U(0x120) 168 #define CTX_FP_Q19 U(0x130) 169 #define CTX_FP_Q20 U(0x140) 170 #define CTX_FP_Q21 U(0x150) 171 #define CTX_FP_Q22 U(0x160) 172 #define CTX_FP_Q23 U(0x170) 173 #define CTX_FP_Q24 U(0x180) 174 #define CTX_FP_Q25 U(0x190) 175 #define CTX_FP_Q26 U(0x1a0) 176 #define CTX_FP_Q27 U(0x1b0) 177 #define CTX_FP_Q28 U(0x1c0) 178 #define CTX_FP_Q29 U(0x1d0) 179 #define CTX_FP_Q30 U(0x1e0) 180 #define CTX_FP_Q31 U(0x1f0) 181 #define CTX_FP_FPSR U(0x200) 182 #define CTX_FP_FPCR U(0x208) 183 #if CTX_INCLUDE_AARCH32_REGS 184 #define CTX_FP_FPEXC32_EL2 U(0x210) 185 #define CTX_FPREGS_END U(0x220) /* Align to the next 16 byte boundary */ 186 #else 187 #define CTX_FPREGS_END U(0x210) /* Align to the next 16 byte boundary */ 188 #endif 189 #else 190 #define CTX_FPREGS_END U(0) 191 #endif 192 193 /******************************************************************************* 194 * Registers related to CVE-2018-3639 195 ******************************************************************************/ 196 #define CTX_CVE_2018_3639_OFFSET (CTX_FPREGS_OFFSET + CTX_FPREGS_END) 197 #define CTX_CVE_2018_3639_DISABLE U(0) 198 #define CTX_CVE_2018_3639_END U(0x10) /* Align to the next 16 byte boundary */ 199 200 /******************************************************************************* 201 * Registers related to ARMv8.3-PAuth. 202 ******************************************************************************/ 203 #define CTX_PAUTH_REGS_OFFSET (CTX_CVE_2018_3639_OFFSET + CTX_CVE_2018_3639_END) 204 #if CTX_INCLUDE_PAUTH_REGS 205 #define CTX_PACIAKEY_LO U(0x0) 206 #define CTX_PACIAKEY_HI U(0x8) 207 #define CTX_PACIBKEY_LO U(0x10) 208 #define CTX_PACIBKEY_HI U(0x18) 209 #define CTX_PACDAKEY_LO U(0x20) 210 #define CTX_PACDAKEY_HI U(0x28) 211 #define CTX_PACDBKEY_LO U(0x30) 212 #define CTX_PACDBKEY_HI U(0x38) 213 #define CTX_PACGAKEY_LO U(0x40) 214 #define CTX_PACGAKEY_HI U(0x48) 215 #define CTX_PAUTH_REGS_END U(0x50) /* Align to the next 16 byte boundary */ 216 #else 217 #define CTX_PAUTH_REGS_END U(0) 218 #endif /* CTX_INCLUDE_PAUTH_REGS */ 219 220 #ifndef __ASSEMBLER__ 221 222 #include <stdint.h> 223 224 #include <lib/cassert.h> 225 226 /* 227 * Common constants to help define the 'cpu_context' structure and its 228 * members below. 229 */ 230 #define DWORD_SHIFT U(3) 231 #define DEFINE_REG_STRUCT(name, num_regs) \ 232 typedef struct name { \ 233 uint64_t _regs[num_regs]; \ 234 } __aligned(16) name##_t 235 236 /* Constants to determine the size of individual context structures */ 237 #define CTX_GPREG_ALL (CTX_GPREGS_END >> DWORD_SHIFT) 238 #define CTX_SYSREG_ALL (CTX_SYSREGS_END >> DWORD_SHIFT) 239 #if CTX_INCLUDE_FPREGS 240 # define CTX_FPREG_ALL (CTX_FPREGS_END >> DWORD_SHIFT) 241 #endif 242 #define CTX_EL3STATE_ALL (CTX_EL3STATE_END >> DWORD_SHIFT) 243 #define CTX_CVE_2018_3639_ALL (CTX_CVE_2018_3639_END >> DWORD_SHIFT) 244 #if CTX_INCLUDE_PAUTH_REGS 245 # define CTX_PAUTH_REGS_ALL (CTX_PAUTH_REGS_END >> DWORD_SHIFT) 246 #endif 247 248 /* 249 * AArch64 general purpose register context structure. Usually x0-x18, 250 * lr are saved as the compiler is expected to preserve the remaining 251 * callee saved registers if used by the C runtime and the assembler 252 * does not touch the remaining. But in case of world switch during 253 * exception handling, we need to save the callee registers too. 254 */ 255 DEFINE_REG_STRUCT(gp_regs, CTX_GPREG_ALL); 256 257 /* 258 * AArch64 EL1 system register context structure for preserving the 259 * architectural state during switches from one security state to 260 * another in EL1. 261 */ 262 DEFINE_REG_STRUCT(el1_sys_regs, CTX_SYSREG_ALL); 263 264 /* 265 * AArch64 floating point register context structure for preserving 266 * the floating point state during switches from one security state to 267 * another. 268 */ 269 #if CTX_INCLUDE_FPREGS 270 DEFINE_REG_STRUCT(fp_regs, CTX_FPREG_ALL); 271 #endif 272 273 /* 274 * Miscellaneous registers used by EL3 firmware to maintain its state 275 * across exception entries and exits 276 */ 277 DEFINE_REG_STRUCT(el3_state, CTX_EL3STATE_ALL); 278 279 /* Function pointer used by CVE-2018-3639 dynamic mitigation */ 280 DEFINE_REG_STRUCT(cve_2018_3639, CTX_CVE_2018_3639_ALL); 281 282 /* Registers associated to ARMv8.3-PAuth */ 283 #if CTX_INCLUDE_PAUTH_REGS 284 DEFINE_REG_STRUCT(pauth, CTX_PAUTH_REGS_ALL); 285 #endif 286 287 /* 288 * Macros to access members of any of the above structures using their 289 * offsets 290 */ 291 #define read_ctx_reg(ctx, offset) ((ctx)->_regs[(offset) >> DWORD_SHIFT]) 292 #define write_ctx_reg(ctx, offset, val) (((ctx)->_regs[(offset) >> DWORD_SHIFT]) \ 293 = (uint64_t) (val)) 294 295 /* 296 * Top-level context structure which is used by EL3 firmware to 297 * preserve the state of a core at EL1 in one of the two security 298 * states and save enough EL3 meta data to be able to return to that 299 * EL and security state. The context management library will be used 300 * to ensure that SP_EL3 always points to an instance of this 301 * structure at exception entry and exit. Each instance will 302 * correspond to either the secure or the non-secure state. 303 */ 304 typedef struct cpu_context { 305 gp_regs_t gpregs_ctx; 306 el3_state_t el3state_ctx; 307 el1_sys_regs_t sysregs_ctx; 308 #if CTX_INCLUDE_FPREGS 309 fp_regs_t fpregs_ctx; 310 #endif 311 cve_2018_3639_t cve_2018_3639_ctx; 312 #if CTX_INCLUDE_PAUTH_REGS 313 pauth_t pauth_ctx; 314 #endif 315 } cpu_context_t; 316 317 /* Macros to access members of the 'cpu_context_t' structure */ 318 #define get_el3state_ctx(h) (&((cpu_context_t *) h)->el3state_ctx) 319 #if CTX_INCLUDE_FPREGS 320 # define get_fpregs_ctx(h) (&((cpu_context_t *) h)->fpregs_ctx) 321 #endif 322 #define get_sysregs_ctx(h) (&((cpu_context_t *) h)->sysregs_ctx) 323 #define get_gpregs_ctx(h) (&((cpu_context_t *) h)->gpregs_ctx) 324 #define get_cve_2018_3639_ctx(h) (&((cpu_context_t *) h)->cve_2018_3639_ctx) 325 #if CTX_INCLUDE_PAUTH_REGS 326 # define get_pauth_ctx(h) (&((cpu_context_t *) h)->pauth_ctx) 327 #endif 328 329 /* 330 * Compile time assertions related to the 'cpu_context' structure to 331 * ensure that the assembler and the compiler view of the offsets of 332 * the structure members is the same. 333 */ 334 CASSERT(CTX_GPREGS_OFFSET == __builtin_offsetof(cpu_context_t, gpregs_ctx), \ 335 assert_core_context_gp_offset_mismatch); 336 CASSERT(CTX_SYSREGS_OFFSET == __builtin_offsetof(cpu_context_t, sysregs_ctx), \ 337 assert_core_context_sys_offset_mismatch); 338 #if CTX_INCLUDE_FPREGS 339 CASSERT(CTX_FPREGS_OFFSET == __builtin_offsetof(cpu_context_t, fpregs_ctx), \ 340 assert_core_context_fp_offset_mismatch); 341 #endif 342 CASSERT(CTX_EL3STATE_OFFSET == __builtin_offsetof(cpu_context_t, el3state_ctx), \ 343 assert_core_context_el3state_offset_mismatch); 344 CASSERT(CTX_CVE_2018_3639_OFFSET == __builtin_offsetof(cpu_context_t, cve_2018_3639_ctx), \ 345 assert_core_context_cve_2018_3639_offset_mismatch); 346 #if CTX_INCLUDE_PAUTH_REGS 347 CASSERT(CTX_PAUTH_REGS_OFFSET == __builtin_offsetof(cpu_context_t, pauth_ctx), \ 348 assert_core_context_pauth_offset_mismatch); 349 #endif 350 351 /* 352 * Helper macro to set the general purpose registers that correspond to 353 * parameters in an aapcs_64 call i.e. x0-x7 354 */ 355 #define set_aapcs_args0(ctx, x0) do { \ 356 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X0, x0); \ 357 } while (0) 358 #define set_aapcs_args1(ctx, x0, x1) do { \ 359 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X1, x1); \ 360 set_aapcs_args0(ctx, x0); \ 361 } while (0) 362 #define set_aapcs_args2(ctx, x0, x1, x2) do { \ 363 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X2, x2); \ 364 set_aapcs_args1(ctx, x0, x1); \ 365 } while (0) 366 #define set_aapcs_args3(ctx, x0, x1, x2, x3) do { \ 367 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X3, x3); \ 368 set_aapcs_args2(ctx, x0, x1, x2); \ 369 } while (0) 370 #define set_aapcs_args4(ctx, x0, x1, x2, x3, x4) do { \ 371 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X4, x4); \ 372 set_aapcs_args3(ctx, x0, x1, x2, x3); \ 373 } while (0) 374 #define set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5) do { \ 375 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X5, x5); \ 376 set_aapcs_args4(ctx, x0, x1, x2, x3, x4); \ 377 } while (0) 378 #define set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6) do { \ 379 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X6, x6); \ 380 set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5); \ 381 } while (0) 382 #define set_aapcs_args7(ctx, x0, x1, x2, x3, x4, x5, x6, x7) do { \ 383 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X7, x7); \ 384 set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6); \ 385 } while (0) 386 387 /******************************************************************************* 388 * Function prototypes 389 ******************************************************************************/ 390 void el1_sysregs_context_save(el1_sys_regs_t *regs); 391 void el1_sysregs_context_restore(el1_sys_regs_t *regs); 392 #if CTX_INCLUDE_FPREGS 393 void fpregs_context_save(fp_regs_t *regs); 394 void fpregs_context_restore(fp_regs_t *regs); 395 #endif 396 397 #endif /* __ASSEMBLER__ */ 398 399 #endif /* CONTEXT_H */ 400