1 // Copyright 2018 the V8 project authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style license that can be 3 // found in the LICENSE file. 4 5 #ifndef V8_CODEGEN_CPU_FEATURES_H_ 6 #define V8_CODEGEN_CPU_FEATURES_H_ 7 8 #include "src/common/globals.h" 9 10 namespace v8 { 11 12 namespace internal { 13 14 // CPU feature flags. 15 enum CpuFeature { 16 #if V8_TARGET_ARCH_IA32 || V8_TARGET_ARCH_X64 17 SSE4_2, 18 SSE4_1, 19 SSSE3, 20 SSE3, 21 SAHF, 22 AVX, 23 FMA3, 24 BMI1, 25 BMI2, 26 LZCNT, 27 POPCNT, 28 ATOM, 29 30 #elif V8_TARGET_ARCH_ARM 31 // - Standard configurations. The baseline is ARMv6+VFPv2. 32 ARMv7, // ARMv7-A + VFPv3-D32 + NEON 33 ARMv7_SUDIV, // ARMv7-A + VFPv4-D32 + NEON + SUDIV 34 ARMv8, // ARMv8-A (+ all of the above) 35 36 // ARM feature aliases (based on the standard configurations above). 37 VFPv3 = ARMv7, 38 NEON = ARMv7, 39 VFP32DREGS = ARMv7, 40 SUDIV = ARMv7_SUDIV, 41 42 #elif V8_TARGET_ARCH_ARM64 43 JSCVT, 44 45 #elif V8_TARGET_ARCH_MIPS || V8_TARGET_ARCH_MIPS64 46 FPU, 47 FP64FPU, 48 MIPSr1, 49 MIPSr2, 50 MIPSr6, 51 MIPS_SIMD, // MSA instructions 52 53 #elif V8_TARGET_ARCH_PPC || V8_TARGET_ARCH_PPC64 54 FPU, 55 FPR_GPR_MOV, 56 LWSYNC, 57 ISELECT, 58 VSX, 59 MODULO, 60 61 #elif V8_TARGET_ARCH_S390X 62 FPU, 63 DISTINCT_OPS, 64 GENERAL_INSTR_EXT, 65 FLOATING_POINT_EXT, 66 VECTOR_FACILITY, 67 VECTOR_ENHANCE_FACILITY_1, 68 VECTOR_ENHANCE_FACILITY_2, 69 MISC_INSTR_EXT2, 70 #endif 71 72 NUMBER_OF_CPU_FEATURES 73 }; 74 75 // CpuFeatures keeps track of which features are supported by the target CPU. 76 // Supported features must be enabled by a CpuFeatureScope before use. 77 // Example: 78 // if (assembler->IsSupported(SSE3)) { 79 // CpuFeatureScope fscope(assembler, SSE3); 80 // // Generate code containing SSE3 instructions. 81 // } else { 82 // // Generate alternative code. 83 // } 84 class V8_EXPORT_PRIVATE CpuFeatures : public AllStatic { 85 public: Probe(bool cross_compile)86 static void Probe(bool cross_compile) { 87 STATIC_ASSERT(NUMBER_OF_CPU_FEATURES <= kBitsPerInt); 88 if (initialized_) return; 89 initialized_ = true; 90 ProbeImpl(cross_compile); 91 } 92 SupportedFeatures()93 static unsigned SupportedFeatures() { 94 Probe(false); 95 return supported_; 96 } 97 IsSupported(CpuFeature f)98 static bool IsSupported(CpuFeature f) { 99 return (supported_ & (1u << f)) != 0; 100 } 101 102 static inline bool SupportsOptimizer(); 103 104 static inline bool SupportsWasmSimd128(); 105 icache_line_size()106 static inline unsigned icache_line_size() { 107 DCHECK_NE(icache_line_size_, 0); 108 return icache_line_size_; 109 } 110 dcache_line_size()111 static inline unsigned dcache_line_size() { 112 DCHECK_NE(dcache_line_size_, 0); 113 return dcache_line_size_; 114 } 115 116 static void PrintTarget(); 117 static void PrintFeatures(); 118 119 private: 120 friend void V8_EXPORT_PRIVATE FlushInstructionCache(void*, size_t); 121 friend class ExternalReference; 122 // Flush instruction cache. 123 static void FlushICache(void* start, size_t size); 124 125 // Platform-dependent implementation. 126 static void ProbeImpl(bool cross_compile); 127 128 static unsigned supported_; 129 static unsigned icache_line_size_; 130 static unsigned dcache_line_size_; 131 static bool initialized_; 132 DISALLOW_COPY_AND_ASSIGN(CpuFeatures); 133 }; 134 135 } // namespace internal 136 } // namespace v8 137 #endif // V8_CODEGEN_CPU_FEATURES_H_ 138