1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2016-2018 NXP 4 * Copyright 2015, Freescale Semiconductor 5 */ 6 7 #ifndef _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ 8 #define _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ 9 10 #include <linux/kconfig.h> 11 #include <fsl_ddrc_version.h> 12 13 #define CONFIG_STANDALONE_LOAD_ADDR 0x80300000 14 15 /* 16 * Reserve secure memory 17 * To be aligned with MMU block size 18 */ 19 #define CONFIG_SYS_MEM_RESERVE_SECURE (66 * 1024 * 1024) /* 66MB */ 20 #define SPL_TLB_SETBACK 0x1000000 /* 16MB under effective memory top */ 21 22 #ifdef CONFIG_ARCH_LS2080A 23 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } 24 #define SRDS_MAX_LANES 8 25 #define CONFIG_SYS_PAGE_SIZE 0x10000 26 #ifndef L1_CACHE_BYTES 27 #define L1_CACHE_SHIFT 6 28 #define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT) 29 #endif 30 31 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ 32 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ 33 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */ 34 35 /* DDR */ 36 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) 37 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE 38 39 #define CONFIG_SYS_FSL_CCSR_GUR_LE 40 #define CONFIG_SYS_FSL_CCSR_SCFG_LE 41 #define CONFIG_SYS_FSL_ESDHC_LE 42 #define CONFIG_SYS_FSL_IFC_LE 43 #define CONFIG_SYS_FSL_PEX_LUT_LE 44 45 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN 46 47 /* Generic Interrupt Controller Definitions */ 48 #define GICD_BASE 0x06000000 49 #define GICR_BASE 0x06100000 50 51 /* SMMU Defintions */ 52 #define SMMU_BASE 0x05000000 /* GR0 Base */ 53 54 /* SFP */ 55 #define CONFIG_SYS_FSL_SFP_VER_3_4 56 #define CONFIG_SYS_FSL_SFP_LE 57 #define CONFIG_SYS_FSL_SRK_LE 58 59 /* Security Monitor */ 60 #define CONFIG_SYS_FSL_SEC_MON_LE 61 62 /* Secure Boot */ 63 #define CONFIG_ESBC_HDR_LS 64 65 /* DCFG - GUR */ 66 #define CONFIG_SYS_FSL_CCSR_GUR_LE 67 68 /* Cache Coherent Interconnect */ 69 #define CCI_MN_BASE 0x04000000 70 #define CCI_MN_RNF_NODEID_LIST 0x180 71 #define CCI_MN_DVM_DOMAIN_CTL 0x200 72 #define CCI_MN_DVM_DOMAIN_CTL_SET 0x210 73 74 #define CCI_HN_F_0_BASE (CCI_MN_BASE + 0x200000) 75 #define CCI_HN_F_1_BASE (CCI_MN_BASE + 0x210000) 76 #define CCN_HN_F_SAM_CTL 0x8 /* offset on base HN_F base */ 77 #define CCN_HN_F_SAM_NODEID_MASK 0x7f 78 #define CCN_HN_F_SAM_NODEID_DDR0 0x4 79 #define CCN_HN_F_SAM_NODEID_DDR1 0xe 80 81 #define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000) 82 #define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000) 83 #define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000) 84 #define CCI_RN_I_12_BASE (CCI_MN_BASE + 0x8C0000) 85 #define CCI_RN_I_16_BASE (CCI_MN_BASE + 0x900000) 86 #define CCI_RN_I_20_BASE (CCI_MN_BASE + 0x940000) 87 88 #define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10) 89 #define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110) 90 #define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210) 91 92 #define CCI_AUX_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x0500) 93 94 /* TZ Protection Controller Definitions */ 95 #define TZPC_BASE 0x02200000 96 #define TZPCR0SIZE_BASE (TZPC_BASE) 97 #define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800) 98 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) 99 #define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808) 100 #define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C) 101 #define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810) 102 #define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814) 103 #define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818) 104 #define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C) 105 #define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820) 106 107 #define DCSR_CGACRE5 0x700070914ULL 108 #define EPU_EPCMPR5 0x700060914ULL 109 #define EPU_EPCCR5 0x700060814ULL 110 #define EPU_EPSMCR5 0x700060228ULL 111 #define EPU_EPECR5 0x700060314ULL 112 #define EPU_EPCTR5 0x700060a14ULL 113 #define EPU_EPGCR 0x700060000ULL 114 115 #define CONFIG_SYS_FSL_ERRATUM_A008751 116 117 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 118 119 #elif defined(CONFIG_ARCH_LS1088A) 120 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 121 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } 122 #define CONFIG_GICV3 123 #define CONFIG_SYS_PAGE_SIZE 0x10000 124 125 #define SRDS_MAX_LANES 4 126 127 /* TZ Protection Controller Definitions */ 128 #define TZPC_BASE 0x02200000 129 #define TZPCR0SIZE_BASE (TZPC_BASE) 130 #define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800) 131 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) 132 #define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808) 133 #define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C) 134 #define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810) 135 #define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814) 136 #define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818) 137 #define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C) 138 #define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820) 139 140 /* Generic Interrupt Controller Definitions */ 141 #define GICD_BASE 0x06000000 142 #define GICR_BASE 0x06100000 143 144 /* SMMU Defintions */ 145 #define SMMU_BASE 0x05000000 /* GR0 Base */ 146 147 /* DDR */ 148 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) 149 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE 150 151 #define CONFIG_SYS_FSL_CCSR_GUR_LE 152 #define CONFIG_SYS_FSL_CCSR_SCFG_LE 153 #define CONFIG_SYS_FSL_ESDHC_LE 154 #define CONFIG_SYS_FSL_IFC_LE 155 #define CONFIG_SYS_FSL_PEX_LUT_LE 156 157 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN 158 159 /* SFP */ 160 #define CONFIG_SYS_FSL_SFP_VER_3_4 161 #define CONFIG_SYS_FSL_SFP_LE 162 #define CONFIG_SYS_FSL_SRK_LE 163 164 /* Security Monitor */ 165 #define CONFIG_SYS_FSL_SEC_MON_LE 166 167 /* Secure Boot */ 168 #define CONFIG_ESBC_HDR_LS 169 170 /* DCFG - GUR */ 171 #define CONFIG_SYS_FSL_CCSR_GUR_LE 172 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 173 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ 174 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ 175 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */ 176 177 /* LX2160A Soc Support */ 178 #elif defined(CONFIG_ARCH_LX2160A) 179 #define TZPC_BASE 0x02200000 180 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) 181 #if !defined(CONFIG_DM_I2C) 182 #define CONFIG_SYS_I2C 183 #define CONFIG_SYS_I2C_EARLY_INIT 184 #endif 185 #define SRDS_MAX_LANES 8 186 #ifndef L1_CACHE_BYTES 187 #define L1_CACHE_SHIFT 6 188 #define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT) 189 #endif 190 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2 191 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1, 4, 4, 4, 4 } 192 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 193 194 #define CONFIG_SYS_PAGE_SIZE 0x10000 195 196 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ 197 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ 198 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */ 199 200 /* DDR */ 201 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) 202 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE 203 204 #define CONFIG_SYS_FSL_CCSR_GUR_LE 205 #define CONFIG_SYS_FSL_CCSR_SCFG_LE 206 #define CONFIG_SYS_FSL_ESDHC_LE 207 #define CONFIG_SYS_FSL_PEX_LUT_LE 208 209 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN 210 211 /* Generic Interrupt Controller Definitions */ 212 #define GICD_BASE 0x06000000 213 #define GICR_BASE 0x06200000 214 215 /* SMMU Definitions */ 216 #define SMMU_BASE 0x05000000 /* GR0 Base */ 217 218 /* SFP */ 219 #define CONFIG_SYS_FSL_SFP_VER_3_4 220 #define CONFIG_SYS_FSL_SFP_LE 221 #define CONFIG_SYS_FSL_SRK_LE 222 223 /* Security Monitor */ 224 #define CONFIG_SYS_FSL_SEC_MON_LE 225 226 /* Secure Boot */ 227 #define CONFIG_ESBC_HDR_LS 228 229 /* DCFG - GUR */ 230 #define CONFIG_SYS_FSL_CCSR_GUR_LE 231 232 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 233 234 #elif defined(CONFIG_ARCH_LS1028A) 235 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 236 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } 237 #define CONFIG_GICV3 238 #define CONFIG_FSL_TZPC_BP147 239 #define CONFIG_FSL_TZASC_400 240 241 /* TZ Protection Controller Definitions */ 242 #define TZPC_BASE 0x02200000 243 #define TZPCR0SIZE_BASE (TZPC_BASE) 244 #define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800) 245 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) 246 #define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808) 247 #define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C) 248 #define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810) 249 #define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814) 250 #define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818) 251 #define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C) 252 #define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820) 253 254 #define SRDS_MAX_LANES 4 255 256 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ 257 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M */ 258 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */ 259 260 /* Generic Interrupt Controller Definitions */ 261 #define GICD_BASE 0x06000000 262 #define GICR_BASE 0x06040000 263 264 /* SMMU Definitions */ 265 #define SMMU_BASE 0x05000000 /* GR0 Base */ 266 267 /* DDR */ 268 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) 269 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE 270 271 #define CONFIG_SYS_FSL_CCSR_GUR_LE 272 #define CONFIG_SYS_FSL_CCSR_SCFG_LE 273 #define CONFIG_SYS_FSL_ESDHC_LE 274 #define CONFIG_SYS_FSL_PEX_LUT_LE 275 276 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN 277 278 /* SFP */ 279 #define CONFIG_SYS_FSL_SFP_VER_3_4 280 #define CONFIG_SYS_FSL_SFP_LE 281 #define CONFIG_SYS_FSL_SRK_LE 282 283 /* SEC */ 284 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 285 286 /* Security Monitor */ 287 #define CONFIG_SYS_FSL_SEC_MON_LE 288 289 /* Secure Boot */ 290 #define CONFIG_ESBC_HDR_LS 291 292 /* DCFG - GUR */ 293 #define CONFIG_SYS_FSL_CCSR_GUR_LE 294 295 #elif defined(CONFIG_FSL_LSCH2) 296 #define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */ 297 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ 298 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */ 299 300 #define DCSR_DCFG_SBEESR2 0x20140534 301 #define DCSR_DCFG_MBEESR2 0x20140544 302 303 #define CONFIG_SYS_FSL_CCSR_SCFG_BE 304 #define CONFIG_SYS_FSL_ESDHC_BE 305 #define CONFIG_SYS_FSL_WDOG_BE 306 #define CONFIG_SYS_FSL_DSPI_BE 307 #define CONFIG_SYS_FSL_QSPI_BE 308 #define CONFIG_SYS_FSL_CCSR_GUR_BE 309 #define CONFIG_SYS_FSL_PEX_LUT_BE 310 311 /* SoC related */ 312 #ifdef CONFIG_ARCH_LS1043A 313 #define CONFIG_SYS_FMAN_V3 314 #define CONFIG_SYS_FSL_QMAN_V3 315 #define CONFIG_SYS_NUM_FMAN 1 316 #define CONFIG_SYS_NUM_FM1_DTSEC 7 317 #define CONFIG_SYS_NUM_FM1_10GEC 1 318 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) 319 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE 320 321 #define QE_MURAM_SIZE 0x6000UL 322 #define MAX_QE_RISC 1 323 #define QE_NUM_OF_SNUM 28 324 325 #define CONFIG_SYS_FSL_IFC_BE 326 #define CONFIG_SYS_FSL_SFP_VER_3_2 327 #define CONFIG_SYS_FSL_SEC_MON_BE 328 #define CONFIG_SYS_FSL_SFP_BE 329 #define CONFIG_SYS_FSL_SRK_LE 330 #define CONFIG_KEY_REVOCATION 331 332 /* SMMU Defintions */ 333 #define SMMU_BASE 0x09000000 334 335 /* Generic Interrupt Controller Definitions */ 336 #define GICD_BASE 0x01401000 337 #define GICC_BASE 0x01402000 338 #define GICH_BASE 0x01404000 339 #define GICV_BASE 0x01406000 340 #define GICD_SIZE 0x1000 341 #define GICC_SIZE 0x2000 342 #define GICH_SIZE 0x2000 343 #define GICV_SIZE 0x2000 344 #ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN 345 #define GICD_BASE_64K 0x01410000 346 #define GICC_BASE_64K 0x01420000 347 #define GICH_BASE_64K 0x01440000 348 #define GICV_BASE_64K 0x01460000 349 #define GICD_SIZE_64K 0x10000 350 #define GICC_SIZE_64K 0x20000 351 #define GICH_SIZE_64K 0x20000 352 #define GICV_SIZE_64K 0x20000 353 #endif 354 355 #define DCFG_CCSR_SVR 0x1ee00a4 356 #define REV1_0 0x10 357 #define REV1_1 0x11 358 #define GIC_ADDR_BIT 31 359 #define SCFG_GIC400_ALIGN 0x1570188 360 361 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 362 363 #elif defined(CONFIG_ARCH_LS1012A) 364 #define GICD_BASE 0x01401000 365 #define GICC_BASE 0x01402000 366 #define CONFIG_SYS_FSL_SFP_VER_3_2 367 #define CONFIG_SYS_FSL_SEC_MON_BE 368 #define CONFIG_SYS_FSL_SFP_BE 369 #define CONFIG_SYS_FSL_SRK_LE 370 #define CONFIG_KEY_REVOCATION 371 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 372 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) 373 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE 374 375 #elif defined(CONFIG_ARCH_LS1046A) 376 #define CONFIG_SYS_FMAN_V3 377 #define CONFIG_SYS_FSL_QMAN_V3 378 #define CONFIG_SYS_NUM_FMAN 1 379 #define CONFIG_SYS_NUM_FM1_DTSEC 8 380 #define CONFIG_SYS_NUM_FM1_10GEC 2 381 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) 382 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE 383 384 #define CONFIG_SYS_FSL_IFC_BE 385 #define CONFIG_SYS_FSL_SFP_VER_3_2 386 #define CONFIG_SYS_FSL_SEC_MON_BE 387 #define CONFIG_SYS_FSL_SFP_BE 388 #define CONFIG_SYS_FSL_SRK_LE 389 #define CONFIG_KEY_REVOCATION 390 391 /* SMMU Defintions */ 392 #define SMMU_BASE 0x09000000 393 394 /* Generic Interrupt Controller Definitions */ 395 #define GICD_BASE 0x01410000 396 #define GICC_BASE 0x01420000 397 398 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 399 #else 400 #error SoC not defined 401 #endif 402 #endif 403 404 #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ */ 405