1 /* 2 * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch.h> 11 #include <common/tbbr/tbbr_img_def.h> 12 #include <plat/common/common_def.h> 13 14 #define PLATFORM_STACK_SIZE 0x1000 15 16 #define PLATFORM_MAX_CPUS_PER_CLUSTER U(2) 17 #define PLATFORM_CLUSTER_COUNT U(1) 18 #define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER 19 #define PLATFORM_CLUSTER1_CORE_COUNT U(0) 20 21 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT + \ 22 PLATFORM_CLUSTER1_CORE_COUNT) 23 24 #define WARP7_PRIMARY_CPU U(0) 25 26 #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \ 27 PLATFORM_CORE_COUNT) 28 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1 29 30 #define PLAT_MAX_RET_STATE 1 31 #define PLAT_MAX_OFF_STATE 2 32 33 /* Local power state for power domains in Run state. */ 34 #define PLAT_LOCAL_STATE_RUN 0 35 36 /* Local power state for retention. Valid only for CPU power domains */ 37 #define PLAT_LOCAL_STATE_RET 1 38 39 /* 40 * Local power state for OFF/power-down. Valid for CPU and cluster power 41 * domains. 42 */ 43 #define PLAT_LOCAL_STATE_OFF 2 44 45 /* 46 * Macros used to parse state information from State-ID if it is using the 47 * recommended encoding for State-ID. 48 */ 49 #define PLAT_LOCAL_PSTATE_WIDTH 4 50 #define PLAT_LOCAL_PSTATE_MASK ((1 << PLAT_LOCAL_PSTATE_WIDTH) - 1) 51 52 /* 53 * Some data must be aligned on the biggest cache line size in the platform. 54 * This is known only to the platform as it might have a combination of 55 * integrated and external caches. 56 * i.MX7 has a 32 byte cacheline size 57 * i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1, 08/2016 pg 244 58 */ 59 #define CACHE_WRITEBACK_SHIFT 4 60 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 61 62 /* 63 * Partition memory into secure BootROM, OCRAM_S, non-secure DRAM, secure DRAM 64 */ 65 #define BOOT_ROM_BASE 0x00000000 66 #define BOOT_ROM_SIZE 0x00020000 67 68 #define OCRAM_S_BASE 0x00180000 69 #define OCRAM_S_SIZE 0x00008000 70 71 /* Controller maps 2GB, board contains 512 MB. 0x80000000 - 0xa0000000 */ 72 #define DRAM_BASE 0x80000000 73 #define DRAM_SIZE 0x20000000 74 #define DRAM_LIMIT (DRAM_BASE + DRAM_SIZE) 75 76 /* Place OPTEE at minus 32 MB from the end of memory. 0x9e000000 - 0xa0000000 */ 77 #define IMX7_OPTEE_SIZE 0x02000000 78 #define IMX7_OPTEE_BASE (DRAM_LIMIT - IMX7_OPTEE_SIZE) 79 #define IMX7_OPTEE_LIMIT (IMX7_OPTEE_BASE + IMX7_OPTEE_SIZE) 80 81 /* Place ATF directly beneath OPTEE. 0x9df00000 - 0x9e000000 */ 82 #define BL2_RAM_SIZE 0x00100000 83 #define BL2_RAM_BASE (IMX7_OPTEE_BASE - BL2_RAM_SIZE) 84 #define BL2_RAM_LIMIT (BL2_RAM_BASE + BL2_RAM_SIZE) 85 86 /* Optional Mailbox. Only relevant on i.MX7D. 0x9deff000 - 0x9df00000*/ 87 #define SHARED_RAM_SIZE 0x00001000 88 #define SHARED_RAM_BASE (BL2_RAM_BASE - SHARED_RAM_SIZE) 89 #define SHARED_RAM_LIMIT (SHARED_RAM_BASE + SHARED_RAM_SIZE) 90 91 /* Define the absolute location of u-boot 0x87800000 - 0x87900000 */ 92 #define IMX7_UBOOT_SIZE 0x00100000 93 #define IMX7_UBOOT_BASE (DRAM_BASE + 0x7800000) 94 #define IMX7_UBOOT_LIMIT (IMX7_UBOOT_BASE + IMX7_UBOOT_SIZE) 95 96 /* Define FIP image absolute location 0x80000000 - 0x80100000 */ 97 #define IMX7_FIP_SIZE 0x00100000 98 #define IMX7_FIP_BASE (DRAM_BASE) 99 #define IMX7_FIP_LIMIT (IMX7_FIP_BASE + IMX7_FIP_SIZE) 100 101 /* Define FIP image location at 1MB offset */ 102 #define IMX7_FIP_MMC_BASE (1024 * 1024) 103 104 /* Define the absolute location of DTB 0x83000000 - 0x83100000 */ 105 #define IMX7_DTB_SIZE 0x00100000 106 #define IMX7_DTB_BASE (DRAM_BASE + 0x03000000) 107 #define IMX7_DTB_LIMIT (IMX7_DTB_BASE + IMX7_DTB_SIZE) 108 109 /* Define the absolute location of DTB Overlay 0x83100000 - 0x83101000 */ 110 #define IMX7_DTB_OVERLAY_SIZE 0x00001000 111 #define IMX7_DTB_OVERLAY_BASE IMX7_DTB_LIMIT 112 #define IMX7_DTB_OVERLAY_LIMIT (IMX7_DTB_OVERLAY_BASE + \ 113 IMX7_DTB_OVERLAY_SIZE) 114 115 /* 116 * BL2 specific defines. 117 * 118 * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug 119 * size plus a little space for growth. 120 */ 121 #define BL2_BASE BL2_RAM_BASE 122 #define BL2_LIMIT (BL2_RAM_BASE + BL2_RAM_SIZE) 123 124 /* 125 * BL3-2/OPTEE 126 */ 127 # define BL32_BASE IMX7_OPTEE_BASE 128 # define BL32_LIMIT (IMX7_OPTEE_BASE + IMX7_OPTEE_SIZE) 129 130 /* 131 * BL3-3/U-BOOT 132 */ 133 #define BL33_BASE IMX7_UBOOT_BASE 134 #define BL33_LIMIT (IMX7_UBOOT_BASE + IMX7_UBOOT_SIZE) 135 136 /* 137 * ATF's view of memory 138 * 139 * 0xa0000000 +-----------------+ 140 * | DDR | BL32/OPTEE 141 * 0x9e000000 +-----------------+ 142 * | DDR | BL23 ATF 143 * 0x9df00000 +-----------------+ 144 * | DDR | Shared MBOX RAM 145 * 0x9de00000 +-----------------+ 146 * | DDR | Unallocated 147 * 0x87900000 +-----------------+ 148 * | DDR | BL33/U-BOOT 149 * 0x87800000 +-----------------+ 150 * | DDR | Unallocated 151 * 0x83101000 +-----------------+ 152 * | DDR | DTB Overlay 153 * 0x83100000 +-----------------+ 154 * | DDR | DTB 155 * 0x83000000 +-----------------+ 156 * | DDR | Unallocated 157 * 0x80100000 +-----------------+ 158 * | DDR | FIP 159 * 0x80000000 +-----------------+ 160 * | SOC I/0 | 161 * 0x00a00000 +-----------------+ 162 * | OCRAM | Not used 163 * 0x00900000 +-----------------+ 164 * | SOC I/0 | 165 * 0x00188000 +-----------------+ 166 * | OCRAM_S | Not used 167 * 0x00180000 +-----------------+ 168 * | SOC I/0 | 169 * 0x00020000 +-----------------+ 170 * | BootROM | BL1 171 * 0x00000000 +-----------------+ 172 */ 173 174 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 175 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 176 #define MAX_MMAP_REGIONS 10 177 #define MAX_XLAT_TABLES 6 178 #define MAX_IO_DEVICES 2 179 #define MAX_IO_HANDLES 3 180 #define MAX_IO_BLOCK_DEVICES 1U 181 182 /* UART defines */ 183 #if PLAT_WARP7_UART == 1 184 #define PLAT_WARP7_UART_BASE MXC_UART1_BASE 185 #elif PLAT_WARP7_UART == 6 186 #define IMX_UART_DTE 187 #define PLAT_WARP7_UART_BASE MXC_UART6_BASE 188 #else 189 #error "define PLAT_WARP7_UART=1 or PLAT_WARP7_UART=6" 190 #endif 191 192 #define PLAT_IMX7_BOOT_UART_BASE PLAT_WARP7_UART_BASE 193 #define PLAT_IMX7_BOOT_UART_CLK_IN_HZ 24000000 194 #define PLAT_IMX7_CONSOLE_BAUDRATE 115200 195 196 /* MMC defines */ 197 #ifndef PLAT_WARP7_SD 198 #define PLAT_WARP7_SD 3 199 #endif 200 201 #if PLAT_WARP7_SD == 1 202 #define PLAT_WARP7_BOOT_MMC_BASE USDHC1_BASE 203 #endif /* PLAT_WARP7_SD == 1 */ 204 205 #if PLAT_WARP7_SD == 2 206 #define PLAT_WARP7_BOOT_MMC_BASE USDHC2_BASE 207 #endif /* PLAT_WARP7_SD == 2 */ 208 209 #if PLAT_WARP7_SD == 3 210 #define PLAT_WARP7_BOOT_MMC_BASE USDHC3_BASE 211 #endif /* PLAT_WARP7_SD == 3 */ 212 213 /* 214 * System counter 215 */ 216 #define SYS_COUNTER_FREQ_IN_TICKS 8000000 /* 8 MHz */ 217 218 #endif /* PLATFORM_DEF_H */ 219