1 /* 2 * Copyright 2018-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef IMX_IO_MUX_H 8 #define IMX_IO_MUX_H 9 10 #include <stdint.h> 11 #include <lib/utils_def.h> 12 13 /* 14 * i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1, 08/2016 15 * Section 8.2.7 IOMUXC Memory Map/Register Definition 16 */ 17 18 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08_OFFSET 0x0014 19 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09_OFFSET 0x0018 20 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10_OFFSET 0x001C 21 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11_OFFSET 0x0020 22 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12_OFFSET 0x0024 23 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13_OFFSET 0x0028 24 25 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14_OFFSET 0x002C 26 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14_ALT1_SD3_CD_B BIT(0) 27 28 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO15_OFFSET 0x0030 29 30 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA00_OFFSET 0x0034 31 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA01_OFFSET 0x0038 32 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA02_OFFSET 0x003C 33 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA03_OFFSET 0x0040 34 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA04_OFFSET 0x0044 35 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA05_OFFSET 0x0048 36 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA06_OFFSET 0x004C 37 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA07_OFFSET 0x0050 38 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA08_OFFSET 0x0054 39 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA09_OFFSET 0x0058 40 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA10_OFFSET 0x005C 41 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA11_OFFSET 0x0060 42 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA12_OFFSET 0x0064 43 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA13_OFFSET 0x0068 44 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA14_OFFSET 0x006C 45 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA15_OFFSET 0x0070 46 47 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCLK_OFFSET 0x0074 48 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDLE_OFFSET 0x0078 49 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDOE_OFFSET 0x007C 50 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDSHR_OFFSET 0x0080 51 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE0_OFFSET 0x0084 52 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE1_OFFSET 0x0088 53 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE2_OFFSET 0x008C 54 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE3_OFFSET 0x0090 55 56 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDCLK_OFFSET 0x0094 57 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDOE_OFFSET 0x0098 58 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDRL_OFFSET 0x009C 59 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDSP_OFFSET 0x00A0 60 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR0_OFFSET 0x00A4 61 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR1_OFFSET 0x00A8 62 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_COM_OFFSET 0x00AC 63 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_STAT_OFFSET 0x00B0 64 65 #define IOMUXC_SW_MUX_CTL_PAD_LCD_CLK_OFFSET 0x00B4 66 #define IOMUXC_SW_MUX_CTL_PAD_LCD_ENABLE_OFFSET 0x00B8 67 #define IOMUXC_SW_MUX_CTL_PAD_LCD_HSYNC_OFFSET 0x00BC 68 #define IOMUXC_SW_MUX_CTL_PAD_LCD_VSYNC_OFFSET 0x00C0 69 #define IOMUXC_SW_MUX_CTL_PAD_LCD_RESET_OFFSET 0x00C4 70 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA00_OFFSET 0x00C8 71 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA01_OFFSET 0x00CC 72 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA02_OFFSET 0x00D0 73 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA03_OFFSET 0x00D4 74 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA04_OFFSET 0x00D8 75 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA05_OFFSET 0x00DC 76 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA06_OFFSET 0x00E0 77 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA07_OFFSET 0x00E4 78 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA08_OFFSET 0x00E8 79 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA09_OFFSET 0x00EC 80 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA10_OFFSET 0x00F0 81 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA11_OFFSET 0x00F4 82 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA12_OFFSET 0x00F8 83 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA13_OFFSET 0x00FC 84 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA14_OFFSET 0x0100 85 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA15_OFFSET 0x0104 86 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA16_OFFSET 0x0108 87 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA17_OFFSET 0x010C 88 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA18_OFFSET 0x0110 89 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA19_OFFSET 0x0114 90 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA20_OFFSET 0x0118 91 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA21_OFFSET 0x011C 92 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA22_OFFSET 0x0120 93 #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA23_OFFSET 0x0124 94 95 #define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_OFFSET 0x0128 96 #define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_ALT0_UART1_RX_DATA 0x00 97 #define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_ALT1_I2C1_SCL BIT(0) 98 #define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_ALT2_PMIC_READY BIT(1) 99 #define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_ALT3_ECSPI1_SS1 (BIT(1) | BIT(0)) 100 #define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_ALT4_ENET2_1588_EVENT0_IN BIT(3) 101 #define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_ALT5_GPIO4_IO0 (BIT(2) | BIT(0)) 102 #define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_ALT6_ENET1_MDIO (BIT(2) | BIT(1)) 103 #define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_SION BIT(3) 104 105 #define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_OFFSET 0x012C 106 #define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_ALT0_UART1_TX_DATA 0x00 107 #define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_ALT1_I2C1_SDA BIT(0) 108 #define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_ALT2_SAI3_MCLK BIT(1) 109 #define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_ALT3_ECSPI1_SS2 (BIT(1) | BIT(0)) 110 #define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_ALT4_ENET2_1588_EVENT0_OUT BIT(3) 111 #define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_ALT5_GPIO4_IO1 (BIT(2) | BIT(0)) 112 #define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_ALT6_ENET1_MDC (BIT(2) | BIT(1)) 113 #define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_SION BIT(3) 114 115 #define IOMUXC_SW_MUX_CTL_PAD_UART2_RX_DATA_OFFSET 0x0130 116 #define IOMUXC_SW_MUX_CTL_PAD_UART2_TX_DATA_OFFSET 0x0134 117 #define IOMUXC_SW_MUX_CTL_PAD_UART3_RX_DATA_OFFSET 0x0138 118 #define IOMUXC_SW_MUX_CTL_PAD_UART3_TX_DATA_OFFSET 0x013C 119 #define IOMUXC_SW_MUX_CTL_PAD_UART3_RTS_B_OFFSET 0x0140 120 #define IOMUXC_SW_MUX_CTL_PAD_UART3_CTS_B_OFFSET 0x0144 121 122 #define IOMUXC_SW_MUX_CTL_PAD_I2C1_SCL_OFFSET 0x0148 123 #define IOMUXC_SW_MUX_CTL_PAD_I2C1_SDA_OFFSET 0x014C 124 #define IOMUXC_SW_MUX_CTL_PAD_I2C2_SCL_OFFSET 0x0150 125 #define IOMUXC_SW_MUX_CTL_PAD_I2C2_SDA_OFFSET 0x0154 126 #define IOMUXC_SW_MUX_CTL_PAD_I2C3_SCL_OFFSET 0x0158 127 #define IOMUXC_SW_MUX_CTL_PAD_I2C3_SDA_OFFSET 0x015C 128 129 #define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_OFFSET 0x0160 130 #define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_ALT0_I2C4_SCL 0x0 131 #define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_ALT1_UART5_RX_DATA BIT(0) 132 #define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_ALT2_WDOG4_WDOG_B BIT(1) 133 #define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_ALT3_CSI_PIXCLK (BIT(1) | BIT(0)) 134 #define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_ALT4_USB_OTG1_ID BIT(2) 135 #define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_ALT5_GPIO4_IO14 (BIT(2) | BIT(0)) 136 #define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_ALT6_EPDC_VCOM0 (BIT(2) | BIT(1)) 137 138 #define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_OFFSET 0x0164 139 #define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_ALT0_I2C4_SDA 0x0 140 #define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_ALT1_UART5_TX_DATA BIT(0) 141 #define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_ALT2_WDOG4_WDOG_RST_B_DEB BIT(1) 142 #define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_ALT3_CSI_MCLK (BIT(1) | BIT(0)) 143 #define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_ALT4_USB_OTG2_ID BIT(2) 144 #define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_ALT5_GPIO4_IO15 (BIT(1) | BIT(0)) 145 #define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_ALT6_EPDC_VCOM1 (BIT(2) | BIT(1)) 146 147 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_OFFSET 0x0168 148 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_ALT0_ECSPI1_SCLK 0x00 149 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_ALT1_UART6_RX_DATA BIT(0) 150 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_ALT2_SD2_DATA4 BIT(1) 151 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_ALT3_CSI_DATA2 (BIT(1) | BIT(0)) 152 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_ALT5_GPIO4_IO16 (BIT(2) | BIT(0)) 153 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_ALT6_EPDC_PWR_COM (BIT(2) | (BIT(1)) 154 155 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_OFFSET 0x016C 156 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_ALT0_ECSPI1_MOSI 0x00 157 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_ALT1_UART6_TX_DATA BIT(0) 158 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_ALT2_SD2_DATA5 BIT(1) 159 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_ALT3_CSI_DATA3 (BIT(1) | BIT(0)) 160 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_ALT5_GPIO4_IO17 (BIT(2) | BIT(0)) 161 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_ALT6_EPDC_PWR_STAT (BIT(2) | (BIT(1)) 162 163 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MISO_OFFSET 0x0170 164 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SS0_OFFSET 0x0174 165 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SCLK_OFFSET 0x0178 166 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MOSI_OFFSET 0x017C 167 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MISO_OFFSET 0x0180 168 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SS0_OFFSET 0x0184 169 170 #define IOMUXC_SW_MUX_CTL_PAD_SD1_CD_B_OFFSET 0x0188 171 #define IOMUXC_SW_MUX_CTL_PAD_SD1_WP_OFFSET 0x018C 172 #define IOMUXC_SW_MUX_CTL_PAD_SD1_RESET_B_OFFSET 0x0190 173 #define IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_OFFSET 0x0194 174 #define IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_OFFSET 0x0198 175 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_OFFSET 0x019C 176 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_OFFSET 0x01A0 177 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_OFFSET 0x01A4 178 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_OFFSET 0x01A8 179 #define IOMUXC_SW_MUX_CTL_PAD_SD2_CD_B_OFFSET 0x01AC 180 #define IOMUXC_SW_MUX_CTL_PAD_SD2_WP_OFFSET 0x01B0 181 #define IOMUXC_SW_MUX_CTL_PAD_SD2_RESET_B_OFFSET 0x01B4 182 #define IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_OFFSET 0x01B8 183 #define IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_OFFSET 0x01BC 184 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_OFFSET 0x01C0 185 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_OFFSET 0x01C4 186 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_OFFSET 0x01C8 187 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_OFFSET 0x01CC 188 189 #define IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_OFFSET 0x01D0 190 #define IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_OFFSET 0x01D4 191 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_OFFSET 0x01D8 192 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_OFFSET 0x01DC 193 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_OFFSET 0x01E0 194 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_OFFSET 0x01E4 195 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_OFFSET 0x01E8 196 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_OFFSET 0x01EC 197 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_OFFSET 0x01F0 198 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_OFFSET 0x01F4 199 #define IOMUXC_SW_MUX_CTL_PAD_SD3_STROBE_OFFSET 0x01F8 200 #define IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_B_OFFSET 0x01FC 201 202 #define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_DATA_OFFSET 0x0200 203 #define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_BCLK_OFFSET 0x0204 204 #define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_SYNC_OFFSET 0x0208 205 #define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_DATA_OFFSET 0x020C 206 #define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_SYNC_OFFSET 0x0210 207 #define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_BCLK_OFFSET 0x0214 208 #define IOMUXC_SW_MUX_CTL_PAD_SAI1_MCLK_OFFSET 0x0218 209 #define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_SYNC_OFFSET 0x021C 210 #define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_BCLK_OFFSET 0x0220 211 #define IOMUXC_SW_MUX_CTL_PAD_SAI2_RX_DATA_OFFSET 0x0224 212 #define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_DATA_OFFSET 0x0228 213 214 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD0_OFFSET 0x022C 215 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD1_OFFSET 0x0230 216 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD2_OFFSET 0x0234 217 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD3_OFFSET 0x0238 218 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RX_CTL_OFFSET 0x023C 219 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RXC_OFFSET 0x0240 220 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD0_OFFSET 0x0244 221 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD1_OFFSET 0x0248 222 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD2_OFFSET 0x024C 223 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD3_OFFSET 0x0250 224 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TX_CTL_OFFSET 0x0254 225 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TXC_OFFSET 0x0258 226 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK_OFFSET 0x025C 227 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_CLK_OFFSET 0x0260 228 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_CRS_OFFSET 0x0264 229 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_COL_OFFSET 0x0268 230 231 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_OFFSET 0x026C 232 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_OFFSET 0x0270 233 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_OFFSET 0x0274 234 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_OFFSET 0x0278 235 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_OFFSET 0x027C 236 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_OFFSET 0x0280 237 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14_OFFSET 0x0284 238 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15_OFFSET 0x0288 239 240 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_OFFSET 0x028C 241 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_OFFSET 0x0290 242 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_OFFSET 0x0294 243 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_OFFSET 0x0298 244 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_OFFSET 0x029C 245 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_OFFSET 0x02A0 246 247 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA00_OFFSET 0x02A4 248 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA01_OFFSET 0x02A8 249 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA02_OFFSET 0x02AC 250 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA03_OFFSET 0x02B0 251 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA04_OFFSET 0x02B4 252 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA05_OFFSET 0x02B8 253 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA06_OFFSET 0x02BC 254 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA07_OFFSET 0x02C0 255 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA08_OFFSET 0x02C4 256 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA09_OFFSET 0x02C8 257 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA10_OFFSET 0x02CC 258 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA11_OFFSET 0x02D0 259 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA12_OFFSET 0x02D4 260 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA13_OFFSET 0x02D8 261 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA14_OFFSET 0x02DC 262 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA15_OFFSET 0x02E0 263 264 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCLK_OFFSET 0x02E4 265 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDLE_OFFSET 0x02E8 266 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDOE_OFFSET 0x02EC 267 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDSHR_OFFSET 0x02F0 268 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE0_OFFSET 0x02F4 269 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE1_OFFSET 0x02F8 270 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE2_OFFSET 0x02FC 271 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE3_OFFSET 0x0300 272 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDCLK_OFFSET 0x0304 273 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDOE_OFFSET 0x0308 274 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDRL_OFFSET 0x030C 275 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDSP_OFFSET 0x0310 276 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR0_OFFSET 0x0314 277 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR1_OFFSET 0x0318 278 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_COM_OFFSET 0x031C 279 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_STAT_OFFSET 0x0320 280 281 #define IOMUXC_SW_PAD_CTL_PAD_LCD_CLK_OFFSET 0x0324 282 #define IOMUXC_SW_PAD_CTL_PAD_LCD_ENABLE_OFFSET 0x0328 283 #define IOMUXC_SW_PAD_CTL_PAD_LCD_HSYNC_OFFSET 0x032C 284 #define IOMUXC_SW_PAD_CTL_PAD_LCD_VSYNC_OFFSET 0x0330 285 #define IOMUXC_SW_PAD_CTL_PAD_LCD_RESET_OFFSET 0x0334 286 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA00_OFFSET 0x0338 287 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA01_OFFSET 0x033C 288 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA02_OFFSET 0x0340 289 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA03_OFFSET 0x0344 290 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA04_OFFSET 0x0348 291 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA05_OFFSET 0x034C 292 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA06_OFFSET 0x0350 293 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA07_OFFSET 0x0354 294 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA08_OFFSET 0x0358 295 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA09_OFFSET 0x035C 296 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA10_OFFSET 0x0360 297 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA11_OFFSET 0x0364 298 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA12_OFFSET 0x0368 299 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA13_OFFSET 0x036C 300 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA14_OFFSET 0x0370 301 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA15_OFFSET 0x0374 302 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA16_OFFSET 0x0378 303 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA17_OFFSET 0x037C 304 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA18_OFFSET 0x0380 305 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA19_OFFSET 0x0384 306 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA20_OFFSET 0x0388 307 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA21_OFFSET 0x038C 308 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA22_OFFSET 0x0390 309 #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA23_OFFSET 0x0394 310 #define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_OFFSET 0x0398 311 #define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_DSE_0_X1 0 312 #define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_DSE_1_X4 BIT(0) 313 #define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_DSE_2_X2 BIT(1) 314 #define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_DSE_3_X6 (BIT(1) | BIT(0)) 315 #define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_SRE_FAST 0 316 #define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_SRE_SLOW BIT(2) 317 #define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_HYS_DIS 0 318 #define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_HYS_EN BIT(3) 319 #define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_PE_DIS 0 320 #define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_PE_EN BIT(4) 321 #define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_PS_0_100K_PD 0 322 #define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_PS_1_5K_PU BIT(5) 323 #define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_PS_2_47K_PU BIT(6) 324 #define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_PS_3_100K_PU (BIT(6) | BIT(5)) 325 326 #define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_OFFSET 0x039C 327 #define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_DSE_0_X1 0 328 #define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_DSE_1_X4 BIT(0) 329 #define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_DSE_2_X2 BIT(1) 330 #define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_DSE_3_X6 (BIT(1) | BIT(0)) 331 #define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_SRE_FAST 0 332 #define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_SRE_SLOW BIT(2) 333 #define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_HYS_DIS 0 334 #define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_HYS_EN BIT(3) 335 #define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_PE_DIS 0 336 #define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_PE_EN BIT(4) 337 #define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_PS_0_100K_PD 0 338 #define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_PS_1_5K_PU BIT(5) 339 #define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_PS_2_47K_PU BIT(6) 340 #define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_PS_3_100K_PU (BIT(6) | BIT(5)) 341 342 #define IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA_OFFSET 0x03A0 343 #define IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA_OFFSET 0x03A4 344 #define IOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA_OFFSET 0x03A8 345 #define IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA_OFFSET 0x03AC 346 #define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_B_OFFSET 0x03B0 347 #define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_B_OFFSET 0x03B4 348 349 #define IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL_OFFSET 0x03B8 350 #define IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA_OFFSET 0x03BC 351 #define IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL_OFFSET 0x03C0 352 #define IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA_OFFSET 0x03C4 353 #define IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL_OFFSET 0x03C8 354 #define IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA_OFFSET 0x03CC 355 #define IOMUXC_SW_PAD_CTL_PAD_I2C4_SCL_OFFSET 0x03D0 356 #define IOMUXC_SW_PAD_CTL_PAD_I2C4_SDA_OFFSET 0x03D4 357 358 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_OFFSET 0x03D8 359 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_DSE_0_X1 0 360 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_DSE_1_X4 BIT(0) 361 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_DSE_2_X2 BIT(1) 362 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_DSE_3_X6 (BIT(1) | BIT(0)) 363 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_SRE_FAST 0 364 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_SRE_SLOW BIT(2) 365 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_HYS_DIS 0 366 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_HYS_EN BIT(3) 367 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PE_DIS 0 368 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PE_EN BIT(4) 369 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PS_0_100K_PD 0 370 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PS_1_5K_PU BIT(5) 371 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PS_2_47K_PU BIT(6) 372 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PS_3_100K_PU (BIT(6) | BIT(5)) 373 374 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_OFFSET 0x03DC 375 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_DSE_0_X1 0 376 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_DSE_1_X4 BIT(0) 377 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_DSE_2_X2 BIT(1) 378 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_DSE_3_X6 (BIT(1) | BIT(0)) 379 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_SRE_FAST 0 380 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_SRE_SLOW BIT(2) 381 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_HYS_DIS 0 382 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_HYS_EN BIT(3) 383 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PE_DIS 0 384 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PE_EN BIT(4) 385 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PS_0_100K_PD 0 386 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PS_1_5K_PU BIT(5) 387 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PS_2_47K_PU BIT(6) 388 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PS_3_100K_PU (BIT(6) | BIT(5)) 389 390 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO_OFFSET 0x03E0 391 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0_OFFSET 0x03E4 392 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK_OFFSET 0x03E8 393 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI_OFFSET 0x03EC 394 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO_OFFSET 0x03F0 395 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0_OFFSET 0x03F4 396 397 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CD_B_OFFSET 0x03F8 398 #define IOMUXC_SW_PAD_CTL_PAD_SD1_WP_OFFSET 0x03FC 399 #define IOMUXC_SW_PAD_CTL_PAD_SD1_RESET_B_OFFSET 0x0400 400 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_OFFSET 0x0404 401 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_OFFSET 0x0408 402 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_OFFSET 0x040C 403 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_OFFSET 0x0410 404 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_OFFSET 0x0414 405 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_OFFSET 0x0418 406 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CD_B_OFFSET 0x041C 407 #define IOMUXC_SW_PAD_CTL_PAD_SD2_WP_OFFSET 0x0420 408 #define IOMUXC_SW_PAD_CTL_PAD_SD2_RESET_B_OFFSET 0x0424 409 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_OFFSET 0x0428 410 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_OFFSET 0x042C 411 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_OFFSET 0x0430 412 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_OFFSET 0x0434 413 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_OFFSET 0x0438 414 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_OFFSET 0x043C 415 416 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_OFFSET 0x0440 417 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_OFFSET 0x0444 418 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_OFFSET 0x0448 419 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_OFFSET 0x044C 420 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_OFFSET 0x0450 421 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_OFFSET 0x0454 422 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_OFFSET 0x0458 423 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_OFFSET 0x045C 424 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_OFFSET 0x0460 425 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_OFFSET 0x0464 426 #define IOMUXC_SW_PAD_CTL_PAD_SD3_STROBE_OFFSET 0x0468 427 #define IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_B_OFFSET 0x046C 428 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DSE_0_X1 0 429 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DSE_1_X4 BIT(0) 430 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DSE_2_X2 BIT(1) 431 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DSE_3_X6 (BIT(1) | BIT(0)) 432 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DSE_1_X4 BIT(0) 433 #define IOMUXC_SW_PAD_CTL_PAD_SD3_SLEW_SLOW BIT(2) 434 #define IOMUXC_SW_PAD_CTL_PAD_SD3_SLEW_FAST 0 435 #define IOMUXC_SW_PAD_CTL_PAD_SD3_HYS BIT(3) 436 #define IOMUXC_SW_PAD_CTL_PAD_SD3_PE BIT(4) 437 #define IOMUXC_SW_PAD_CTL_PAD_SD3_PD_100K (0 << 5) 438 #define IOMUXC_SW_PAD_CTL_PAD_SD3_PU_5K (1 << 5) 439 #define IOMUXC_SW_PAD_CTL_PAD_SD3_PU_47K (2 << 5) 440 #define IOMUXC_SW_PAD_CTL_PAD_SD3_PU_100K (3 << 5) 441 442 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_DATA_OFFSET 0x0470 443 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_BCLK_OFFSET 0x0474 444 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_SYNC_OFFSET 0x0478 445 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_DATA_OFFSET 0x047C 446 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_SYNC_OFFSET 0x0480 447 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_BCLK_OFFSET 0x0484 448 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_MCLK_OFFSET 0x0488 449 #define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_SYNC_OFFSET 0x048C 450 #define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_BCLK_OFFSET 0x0490 451 #define IOMUXC_SW_PAD_CTL_PAD_SAI2_RX_DATA_OFFSET 0x0494 452 #define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_DATA_OFFSET 0x0498 453 454 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD0_OFFSET 0x049C 455 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD1_OFFSET 0x04A0 456 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD2_OFFSET 0x04A4 457 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3_OFFSET 0x04A8 458 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RX_CTL_OFFSET 0x04AC 459 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RXC_OFFSET 0x04B0 460 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD0_OFFSET 0x04B4 461 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD1_OFFSET 0x04B8 462 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD2_OFFSET 0x04BC 463 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD3_OFFSET 0x04C0 464 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TX_CTL_OFFSET 0x04C4 465 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TXC_OFFSET 0x04C8 466 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_OFFSET 0x04CC 467 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_OFFSET 0x04D0 468 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_OFFSET 0x04D4 469 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_OFFSET 0x04D8 470 471 #define IOMUXC_FLEXCAN1_RX_SELECT_INPUT_OFFSET 0x04DC 472 #define IOMUXC_FLEXCAN2_RX_SELECT_INPUT_OFFSET 0x04E0 473 474 #define IOMUXC_CCM_EXT_CLK_1_SELECT_INPUT_OFFSET 0x04E4 475 #define IOMUXC_CCM_EXT_CLK_2_SELECT_INPUT_OFFSET 0x04E8 476 #define IOMUXC_CCM_EXT_CLK_3_SELECT_INPUT_OFFSET 0x04EC 477 #define IOMUXC_CCM_EXT_CLK_4_SELECT_INPUT_OFFSET 0x04F0 478 479 #define IOMUXC_CCM_PMIC_READY_SELECT_INPUT_OFFSET 0x04F4 480 481 #define IOMUXC_CSI_DATA2_SELECT_INPUT_OFFSET 0x04F8 482 #define IOMUXC_CSI_DATA3_SELECT_INPUT_OFFSET 0x04FC 483 #define IOMUXC_CSI_DATA4_SELECT_INPUT_OFFSET 0x0500 484 #define IOMUXC_CSI_DATA5_SELECT_INPUT_OFFSET 0x0504 485 #define IOMUXC_CSI_DATA6_SELECT_INPUT_OFFSET 0x0508 486 #define IOMUXC_CSI_DATA7_SELECT_INPUT_OFFSET 0x050C 487 #define IOMUXC_CSI_DATA8_SELECT_INPUT_OFFSET 0x0510 488 #define IOMUXC_CSI_DATA9_SELECT_INPUT_OFFSET 0x0514 489 #define IOMUXC_CSI_HSYNC_SELECT_INPUT_OFFSET 0x0518 490 #define IOMUXC_CSI_PIXCLK_SELECT_INPUT_OFFSET 0x051C 491 #define IOMUXC_CSI_VSYNC_SELECT_INPUT_OFFSET 0x0520 492 493 #define IOMUXC_ECSPI1_SCLK_SELECT_INPUT_OFFSET 0x0524 494 #define IOMUXC_ECSPI1_MISO_SELECT_INPUT_OFFSET 0x0528 495 #define IOMUXC_ECSPI1_MOSI_SELECT_INPUT_OFFSET 0x052C 496 #define IOMUXC_ECSPI1_SS0_B_SELECT_INPUT_OFFSET 0x0530 497 #define IOMUXC_ECSPI2_SCLK_SELECT_INPUT_OFFSET 0x0534 498 #define IOMUXC_ECSPI2_MISO_SELECT_INPUT_OFFSET 0x0538 499 #define IOMUXC_ECSPI2_MOSI_SELECT_INPUT_OFFSET 0x053C 500 #define IOMUXC_ECSPI2_SS0_B_SELECT_INPUT_OFFSET 0x0540 501 #define IOMUXC_ECSPI3_SCLK_SELECT_INPUT_OFFSET 0x0544 502 #define IOMUXC_ECSPI3_MISO_SELECT_INPUT_OFFSET 0x0548 503 #define IOMUXC_ECSPI3_MOSI_SELECT_INPUT_OFFSET 0x054C 504 #define IOMUXC_ECSPI3_SS0_B_SELECT_INPUT_OFFSET 0x0550 505 #define IOMUXC_ECSPI4_SCLK_SELECT_INPUT_OFFSET 0x0554 506 #define IOMUXC_ECSPI4_MISO_SELECT_INPUT_OFFSET 0x0558 507 #define IOMUXC_ECSPI4_MOSI_SELECT_INPUT_OFFSET 0x055C 508 #define IOMUXC_ECSPI4_SS0_B_SELECT_INPUT_OFFSET 0x0560 509 510 #define IOMUXC_CCM_ENET1_REF_CLK_SELECT_INPUT_OFFSET 0x0564 511 #define IOMUXC_ENET1_MDIO_SELECT_INPUT_OFFSET 0x0568 512 #define IOMUXC_ENET1_RX_CLK_SELECT_INPUT_OFFSET 0x056C 513 #define IOMUXC_CCM_ENET2_REF_CLK_SELECT_INPUT_OFFSET 0x0570 514 #define IOMUXC_ENET2_MDIO_SELECT_INPUT_OFFSET 0x0574 515 #define IOMUXC_ENET2_RX_CLK_SELECT_INPUT_OFFSET 0x0578 516 517 #define IOMUXC_EPDC_PWR_IRQ_SELECT_INPUT_OFFSET 0x057C 518 #define IOMUXC_EPDC_PWR_STAT_SELECT_INPUT_OFFSET 0x0580 519 520 #define IOMUXC_FLEXTIMER1_CH0_SELECT_INPUT_OFFSET 0x0584 521 #define IOMUXC_FLEXTIMER1_CH1_SELECT_INPUT_OFFSET 0x0588 522 #define IOMUXC_FLEXTIMER1_CH2_SELECT_INPUT_OFFSET 0x058C 523 #define IOMUXC_FLEXTIMER1_CH3_SELECT_INPUT_OFFSET 0x0590 524 #define IOMUXC_FLEXTIMER1_CH4_SELECT_INPUT_OFFSET 0x0594 525 #define IOMUXC_FLEXTIMER1_CH5_SELECT_INPUT_OFFSET 0x0598 526 #define IOMUXC_FLEXTIMER1_CH6_SELECT_INPUT_OFFSET 0x059C 527 #define IOMUXC_FLEXTIMER1_CH7_SELECT_INPUT_OFFSET 0x05A0 528 #define IOMUXC_FLEXTIMER1_PHA_SELECT_INPUT_OFFSET 0x05A4 529 #define IOMUXC_FLEXTIMER1_PHB_SELECT_INPUT_OFFSET 0x05A8 530 #define IOMUXC_FLEXTIMER2_CH0_SELECT_INPUT_OFFSET 0x05AC 531 #define IOMUXC_FLEXTIMER2_CH1_SELECT_INPUT_OFFSET 0x05B0 532 #define IOMUXC_FLEXTIMER2_CH2_SELECT_INPUT_OFFSET 0x05B4 533 #define IOMUXC_FLEXTIMER2_CH3_SELECT_INPUT_OFFSET 0x05B8 534 #define IOMUXC_FLEXTIMER2_CH4_SELECT_INPUT_OFFSET 0x05BC 535 #define IOMUXC_FLEXTIMER2_CH5_SELECT_INPUT_OFFSET 0x05C0 536 #define IOMUXC_FLEXTIMER2_CH6_SELECT_INPUT_OFFSET 0x05C4 537 #define IOMUXC_FLEXTIMER2_CH7_SELECT_INPUT_OFFSET 0x05C8 538 #define IOMUXC_FLEXTIMER2_PHA_SELECT_INPUT_OFFSET 0x05CC 539 #define IOMUXC_FLEXTIMER2_PHB_SELECT_INPUT_OFFSET 0x05D0 540 541 #define IOMUXC_I2C1_SCL_SELECT_INPUT_OFFSET 0x05D4 542 #define IOMUXC_I2C1_SDA_SELECT_INPUT_OFFSET 0x05D8 543 #define IOMUXC_I2C2_SCL_SELECT_INPUT_OFFSET 0x05DC 544 #define IOMUXC_I2C2_SDA_SELECT_INPUT_OFFSET 0x05E0 545 #define IOMUXC_I2C3_SCL_SELECT_INPUT_OFFSET 0x05E4 546 #define IOMUXC_I2C3_SDA_SELECT_INPUT_OFFSET 0x05E8 547 #define IOMUXC_I2C4_SCL_SELECT_INPUT_OFFSET 0x05EC 548 #define IOMUXC_I2C4_SDA_SELECT_INPUT_OFFSET 0x05F0 549 550 #define IOMUXC_KPP_COL0_SELECT_INPUT_OFFSET 0x05F4 551 #define IOMUXC_KPP_COL1_SELECT_INPUT_OFFSET 0x05F8 552 #define IOMUXC_KPP_COL2_SELECT_INPUT_OFFSET 0x05FC 553 #define IOMUXC_KPP_COL3_SELECT_INPUT_OFFSET 0x0600 554 #define IOMUXC_KPP_COL4_SELECT_INPUT_OFFSET 0x0604 555 #define IOMUXC_KPP_COL5_SELECT_INPUT_OFFSET 0x0608 556 #define IOMUXC_KPP_COL6_SELECT_INPUT_OFFSET 0x060C 557 #define IOMUXC_KPP_COL7_SELECT_INPUT_OFFSET 0x0610 558 #define IOMUXC_KPP_ROW0_SELECT_INPUT_OFFSET 0x0614 559 #define IOMUXC_KPP_ROW1_SELECT_INPUT_OFFSET 0x0618 560 #define IOMUXC_KPP_ROW2_SELECT_INPUT_OFFSET 0x061C 561 #define IOMUXC_KPP_ROW3_SELECT_INPUT_OFFSET 0x0620 562 #define IOMUXC_KPP_ROW4_SELECT_INPUT_OFFSET 0x0624 563 #define IOMUXC_KPP_ROW5_SELECT_INPUT_OFFSET 0x0628 564 #define IOMUXC_KPP_ROW6_SELECT_INPUT_OFFSET 0x062C 565 #define IOMUXC_KPP_ROW7_SELECT_INPUT_OFFSET 0x0630 566 567 #define IOMUXC_LCD_BUSY_SELECT_INPUT_OFFSET 0x0634 568 #define IOMUXC_LCD_DATA00_SELECT_INPUT_OFFSET 0x0638 569 #define IOMUXC_LCD_DATA01_SELECT_INPUT_OFFSET 0x063C 570 #define IOMUXC_LCD_DATA02_SELECT_INPUT_OFFSET 0x0640 571 #define IOMUXC_LCD_DATA03_SELECT_INPUT_OFFSET 0x0644 572 #define IOMUXC_LCD_DATA04_SELECT_INPUT_OFFSET 0x0648 573 #define IOMUXC_LCD_DATA05_SELECT_INPUT_OFFSET 0x064C 574 #define IOMUXC_LCD_DATA06_SELECT_INPUT_OFFSET 0x0650 575 #define IOMUXC_LCD_DATA07_SELECT_INPUT_OFFSET 0x0654 576 #define IOMUXC_LCD_DATA08_SELECT_INPUT_OFFSET 0x0658 577 #define IOMUXC_LCD_DATA09_SELECT_INPUT_OFFSET 0x065C 578 #define IOMUXC_LCD_DATA10_SELECT_INPUT_OFFSET 0x0660 579 #define IOMUXC_LCD_DATA11_SELECT_INPUT_OFFSET 0x0664 580 #define IOMUXC_LCD_DATA12_SELECT_INPUT_OFFSET 0x0668 581 #define IOMUXC_LCD_DATA13_SELECT_INPUT_OFFSET 0x066C 582 #define IOMUXC_LCD_DATA14_SELECT_INPUT_OFFSET 0x0670 583 #define IOMUXC_LCD_DATA15_SELECT_INPUT_OFFSET 0x0674 584 #define IOMUXC_LCD_DATA16_SELECT_INPUT_OFFSET 0x0678 585 #define IOMUXC_LCD_DATA17_SELECT_INPUT_OFFSET 0x067C 586 #define IOMUXC_LCD_DATA18_SELECT_INPUT_OFFSET 0x0680 587 #define IOMUXC_LCD_DATA19_SELECT_INPUT_OFFSET 0x0684 588 #define IOMUXC_LCD_DATA20_SELECT_INPUT_OFFSET 0x0688 589 #define IOMUXC_LCD_DATA21_SELECT_INPUT_OFFSET 0x068C 590 #define IOMUXC_LCD_DATA22_SELECT_INPUT_OFFSET 0x0690 591 #define IOMUXC_LCD_DATA23_SELECT_INPUT_OFFSET 0x0694 592 #define IOMUXC_LCD_VSYNC_SELECT_INPUT_OFFSET 0x0698 593 594 #define IOMUXC_SAI1_RX_BCLK_SELECT_INPUT_OFFSET 0x069C 595 #define IOMUXC_SAI1_RX_DATA_SELECT_INPUT_OFFSET 0x06A0 596 #define IOMUXC_SAI1_RX_SYNC_SELECT_INPUT_OFFSET 0x06A4 597 #define IOMUXC_SAI1_TX_BCLK_SELECT_INPUT_OFFSET 0x06A8 598 #define IOMUXC_SAI1_TX_SYNC_SELECT_INPUT_OFFSET 0x06AC 599 #define IOMUXC_SAI2_RX_BCLK_SELECT_INPUT_OFFSET 0x06B0 600 #define IOMUXC_SAI2_RX_DATA_SELECT_INPUT_OFFSET 0x06B4 601 #define IOMUXC_SAI2_RX_SYNC_SELECT_INPUT_OFFSET 0x06B8 602 #define IOMUXC_SAI2_TX_BCLK_SELECT_INPUT_OFFSET 0x06BC 603 #define IOMUXC_SAI2_TX_SYNC_SELECT_INPUT_OFFSET 0x06C0 604 #define IOMUXC_SAI3_RX_BCLK_SELECT_INPUT_OFFSET 0x06C4 605 #define IOMUXC_SAI3_RX_DATA_SELECT_INPUT_OFFSET 0x06C8 606 #define IOMUXC_SAI3_RX_SYNC_SELECT_INPUT_OFFSET 0x06CC 607 #define IOMUXC_SAI3_TX_BCLK_SELECT_INPUT_OFFSET 0x06D0 608 #define IOMUXC_SAI3_TX_SYNC_SELECT_INPUT_OFFSET 0x06D4 609 #define IOMUXC_SDMA_EVENTS0_SELECT_INPUT_OFFSET 0x06D8 610 #define IOMUXC_SDMA_EVENTS1_SELECT_INPUT_OFFSET 0x06DC 611 612 #define IOMUXC_SIM1_PORT1_PD_SELECT_INPUT_OFFSET 0x06E0 613 #define IOMUXC_SIM1_PORT1_TRXD_SELECT_INPUT_OFFSET 0x06E4 614 #define IOMUXC_SIM2_PORT1_PD_SELECT_INPUT_OFFSET 0x06E8 615 #define IOMUXC_SIM2_PORT1_TRXD_SELECT_INPUT_OFFSET 0x06EC 616 617 #define IOMUXC_UART1_RTS_B_SELECT_INPUT_OFFSET 0x06F0 618 #define IOMUXC_UART1_RX_DATA_SELECT_INPUT_OFFSET 0x06F4 619 #define IOMUXC_UART2_RTS_B_SELECT_INPUT_OFFSET 0x06F8 620 #define IOMUXC_UART2_RX_DATA_SELECT_INPUT_OFFSET 0x06FC 621 #define IOMUXC_UART3_RTS_B_SELECT_INPUT_OFFSET 0x0700 622 #define IOMUXC_UART3_RX_DATA_SELECT_INPUT_OFFSET 0x0704 623 #define IOMUXC_UART4_RTS_B_SELECT_INPUT_OFFSET 0x0708 624 #define IOMUXC_UART4_RX_DATA_SELECT_INPUT_OFFSET 0x070C 625 #define IOMUXC_UART5_RTS_B_SELECT_INPUT_OFFSET 0x0710 626 627 #define IOMUXC_UART5_RX_DATA_SELECT_INPUT_OFFSET 0x0714 628 #define IOMUXC_UART5_RX_DATA_SELECT_INPUT_I2C4_SCL_ALT1 0x00 629 #define IOMUXC_UART5_RX_DATA_SELECT_INPUT_I2C4_SDA_ALT1 BIT(0) 630 #define IOMUXC_UART5_RX_DATA_SELECT_INPUT_SAI1_RX_DATA_ALT2 BIT(1) 631 #define IOMUXC_UART5_RX_DATA_SELECT_INPUT_SAI1_TX_BCLK_ALT2 (BIT(1) | BIT(0)) 632 #define IOMUXC_UART5_RX_DATA_SELECT_INPUT_GPIO1_IO06_ALT3 BIT(2) 633 #define IOMUXC_UART5_RX_DATA_SELECT_INPUT_GPIO1_IO07_ALT3 (BIT(2) | BIT(1)) 634 635 #define IOMUXC_UART6_RTS_B_SELECT_INPUT_OFFSET 0x0718 636 #define IOMUXC_UART6_RX_DATA_SELECT_INPUT_OFFSET 0x071C 637 #define IOMUXC_UART7_RTS_B_SELECT_INPUT_OFFSET 0x0720 638 #define IOMUXC_UART7_RX_DATA_SELECT_INPUT_OFFSET 0x0724 639 640 #define IOMUXC_USB_OTG2_OC_SELECT_INPUT_OFFSET 0x0728 641 #define IOMUXC_USB_OTG1_OC_SELECT_INPUT_OFFSET 0x072C 642 #define IOMUXC_USB_OTG2_ID_SELECT_INPUT_OFFSET 0x0730 643 #define IOMUXC_USB_OTG1_ID_SELECT_INPUT_OFFSET 0x0734 644 #define IOMUXC_SD3_CD_B_SELECT_INPUT_OFFSET 0x0738 645 #define IOMUXC_SD3_WP_SELECT_INPUT_OFFSET 0x073C 646 647 /* Pad mux/feature set routines */ 648 649 void imx_io_muxc_set_pad_alt_function(uint32_t pad_mux_offset, uint32_t alt_function); 650 void imx_io_muxc_set_pad_features(uint32_t pad_feature_offset, uint32_t pad_features); 651 652 #endif /* IMX_IO_MUX_H */ 653