| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/ |
| D | AVRRegisterInfo.cpp | 267 unsigned &LoReg, in splitReg()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonCopyToCombine.cpp | 734 unsigned LoReg = LoOperand.getReg(); in emitCombineIR() local
833 unsigned LoReg = LoOperand.getReg(); in emitCombineRR() local
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| D | HexagonFrameLowering.cpp | 827 unsigned LoReg = HRI.getSubReg(Reg, Hexagon::subreg_loreg); in insertCFIInstructionsAt() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonCopyToCombine.cpp | 763 unsigned LoReg = LoOperand.getReg(); in emitCombineIR() local
862 unsigned LoReg = LoOperand.getReg(); in emitCombineRR() local
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| D | HexagonFrameLowering.cpp | 947 unsigned LoReg = HRI.getSubReg(Reg, Hexagon::isub_lo); in insertCFIInstructionsAt() local
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 2137 unsigned LoReg; in Select() local
2184 unsigned SrcReg, LoReg, HiReg; in Select() local
2341 unsigned LoReg, HiReg, ClrReg; in Select() local
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 651 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); in expandBuildPairF64() local
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| D | MipsSEFrameLowering.cpp | 284 unsigned LoReg = I->getOperand(1).getReg(); in expandBuildPairF64() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 813 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); in expandBuildPairF64() local
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| D | MipsSEFrameLowering.cpp | 309 unsigned LoReg = I->getOperand(1).getReg(); in expandBuildPairF64() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstructionSelector.cpp | 362 unsigned LoReg = MRI.createVirtualRegister(RC); in selectG_CONSTANT() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 2923 unsigned LoReg, Opc; in Select() local
2967 unsigned SrcReg, LoReg, HiReg; in Select() local
3096 unsigned LoReg, HiReg, ClrReg; in Select() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/ |
| D | RISCVISelLowering.cpp | 496 unsigned LoReg = MI.getOperand(0).getReg(); in emitSplitF64Pseudo() local
529 unsigned LoReg = MI.getOperand(1).getReg(); in emitBuildPairF64Pseudo() local
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 9053 unsigned LoReg = MI.getOperand(0).getReg(); in EmitInstrWithCustomInserter() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 10385 unsigned LoReg = MI.getOperand(0).getReg(); in EmitInstrWithCustomInserter() local
|