1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) Marvell International Ltd. and its affiliates 4 */ 5 6 #ifndef _MV_DDR_TOPOLOGY_H 7 #define _MV_DDR_TOPOLOGY_H 8 9 #define MAX_CS_NUM 4 10 11 enum mv_ddr_speed_bin { 12 SPEED_BIN_DDR_800D, 13 SPEED_BIN_DDR_800E, 14 SPEED_BIN_DDR_1066E, 15 SPEED_BIN_DDR_1066F, 16 SPEED_BIN_DDR_1066G, 17 SPEED_BIN_DDR_1333F, 18 SPEED_BIN_DDR_1333G, 19 SPEED_BIN_DDR_1333H, 20 SPEED_BIN_DDR_1333J, 21 SPEED_BIN_DDR_1600G, 22 SPEED_BIN_DDR_1600H, 23 SPEED_BIN_DDR_1600J, 24 SPEED_BIN_DDR_1600K, 25 SPEED_BIN_DDR_1866J, 26 SPEED_BIN_DDR_1866K, 27 SPEED_BIN_DDR_1866L, 28 SPEED_BIN_DDR_1866M, 29 SPEED_BIN_DDR_2133K, 30 SPEED_BIN_DDR_2133L, 31 SPEED_BIN_DDR_2133M, 32 SPEED_BIN_DDR_2133N, 33 34 SPEED_BIN_DDR_1333H_EXT, 35 SPEED_BIN_DDR_1600K_EXT, 36 SPEED_BIN_DDR_1866M_EXT 37 }; 38 39 enum mv_ddr_freq { 40 MV_DDR_FREQ_LOW_FREQ, 41 MV_DDR_FREQ_400, 42 MV_DDR_FREQ_533, 43 MV_DDR_FREQ_667, 44 MV_DDR_FREQ_800, 45 MV_DDR_FREQ_933, 46 MV_DDR_FREQ_1066, 47 MV_DDR_FREQ_311, 48 MV_DDR_FREQ_333, 49 MV_DDR_FREQ_467, 50 MV_DDR_FREQ_850, 51 MV_DDR_FREQ_600, 52 MV_DDR_FREQ_300, 53 MV_DDR_FREQ_900, 54 MV_DDR_FREQ_360, 55 MV_DDR_FREQ_1000, 56 MV_DDR_FREQ_LAST, 57 MV_DDR_FREQ_SAR 58 }; 59 60 enum mv_ddr_speed_bin_timing { 61 SPEED_BIN_TRCD, 62 SPEED_BIN_TRP, 63 SPEED_BIN_TRAS, 64 SPEED_BIN_TRC, 65 SPEED_BIN_TRRD1K, 66 SPEED_BIN_TRRD2K, 67 SPEED_BIN_TPD, 68 SPEED_BIN_TFAW1K, 69 SPEED_BIN_TFAW2K, 70 SPEED_BIN_TWTR, 71 SPEED_BIN_TRTP, 72 SPEED_BIN_TWR, 73 SPEED_BIN_TMOD, 74 SPEED_BIN_TXPDLL, 75 SPEED_BIN_TXSDLL 76 }; 77 78 /* ddr bus masks */ 79 #define BUS_MASK_32BIT 0xf 80 #define BUS_MASK_32BIT_ECC 0x1f 81 #define BUS_MASK_16BIT 0x3 82 #define BUS_MASK_16BIT_ECC 0x13 83 #define BUS_MASK_16BIT_ECC_PUP3 0xb 84 #define MV_DDR_64BIT_BUS_MASK 0xff 85 #define MV_DDR_64BIT_ECC_PUP8_BUS_MASK 0x1ff 86 #define MV_DDR_32BIT_ECC_PUP8_BUS_MASK 0x10f 87 88 #define MV_DDR_CS_BITMASK_1CS 0x1 89 #define MV_DDR_CS_BITMASK_2CS 0x3 90 91 #define MV_DDR_ONE_SPHY_PER_DUNIT 1 92 #define MV_DDR_TWO_SPHY_PER_DUNIT 2 93 94 /* source of ddr configuration data */ 95 enum mv_ddr_cfg_src { 96 MV_DDR_CFG_DEFAULT, /* based on data in mv_ddr_topology_map structure */ 97 MV_DDR_CFG_SPD, /* based on data in spd */ 98 MV_DDR_CFG_USER, /* based on data from user */ 99 MV_DDR_CFG_STATIC, /* based on data from user in register-value format */ 100 MV_DDR_CFG_LAST 101 }; 102 103 enum mv_ddr_temperature { 104 MV_DDR_TEMP_LOW, 105 MV_DDR_TEMP_NORMAL, 106 MV_DDR_TEMP_HIGH 107 }; 108 109 enum mv_ddr_timing { 110 MV_DDR_TIM_DEFAULT, 111 MV_DDR_TIM_1T, 112 MV_DDR_TIM_2T 113 }; 114 115 enum mv_ddr_timing_data { 116 MV_DDR_TCK_AVG_MIN, /* sdram min cycle time (t ck avg min) */ 117 MV_DDR_TAA_MIN, /* min cas latency time (t aa min) */ 118 MV_DDR_TRFC1_MIN, /* min refresh recovery delay time (t rfc1 min) */ 119 MV_DDR_TWR_MIN, /* min write recovery time (t wr min) */ 120 MV_DDR_TRCD_MIN, /* min ras to cas delay time (t rcd min) */ 121 MV_DDR_TRP_MIN, /* min row precharge delay time (t rp min) */ 122 MV_DDR_TRC_MIN, /* min active to active/refresh delay time (t rc min) */ 123 MV_DDR_TRAS_MIN, /* min active to precharge delay time (t ras min) */ 124 MV_DDR_TRRD_S_MIN, /* min activate to activate delay time (t rrd_s min), diff bank group */ 125 MV_DDR_TRRD_L_MIN, /* min activate to activate delay time (t rrd_l min), same bank group */ 126 MV_DDR_TCCD_L_MIN, /* min cas to cas delay time (t ccd_l min), same bank group */ 127 MV_DDR_TFAW_MIN, /* min four activate window delay time (t faw min) */ 128 MV_DDR_TWTR_S_MIN, /* min write to read time (t wtr s min), diff bank group */ 129 MV_DDR_TWTR_L_MIN, /* min write to read time (t wtr l min), same bank group */ 130 MV_DDR_TDATA_LAST 131 }; 132 133 enum mv_ddr_electrical_data { 134 MV_DDR_CK_DLY, 135 MV_DDR_PHY_REG3, 136 MV_DDR_ZPRI_DATA, 137 MV_DDR_ZNRI_DATA, 138 MV_DDR_ZPRI_CTRL, 139 MV_DDR_ZNRI_CTRL, 140 MV_DDR_ZPODT_DATA, 141 MV_DDR_ZNODT_DATA, 142 MV_DDR_ZPODT_CTRL, 143 MV_DDR_ZNODT_CTRL, 144 MV_DDR_DIC, 145 MV_DDR_ODT_CFG, 146 MV_DDR_RTT_NOM, 147 MV_DDR_RTT_WR, 148 MV_DDR_RTT_PARK, 149 MV_DDR_EDATA_LAST 150 }; 151 152 /* memory electrical configuration values */ 153 enum mv_ddr_rtt_nom_park_evalue { 154 MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, 155 MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* 60-Ohm; RZQ = 240-Ohm */ 156 MV_DDR_RTT_NOM_PARK_RZQ_DIV2, /* 120-Ohm; RZQ = 240-Ohm */ 157 MV_DDR_RTT_NOM_PARK_RZQ_DIV6, /* 40-Ohm; RZQ = 240-Ohm */ 158 MV_DDR_RTT_NOM_PARK_RZQ_DIV1, /* 240-Ohm; RZQ = 240-Ohm */ 159 MV_DDR_RTT_NOM_PARK_RZQ_DIV5, /* 48-Ohm; RZQ = 240-Ohm */ 160 MV_DDR_RTT_NOM_PARK_RZQ_DIV3, /* 80-Ohm; RZQ = 240-Ohm */ 161 MV_DDR_RTT_NOM_PARK_RZQ_DIV7, /* 34-Ohm; RZQ = 240-Ohm */ 162 MV_DDR_RTT_NOM_PARK_RZQ_LAST 163 }; 164 165 enum mv_ddr_rtt_wr_evalue { 166 MV_DDR_RTT_WR_DYN_ODT_OFF, 167 MV_DDR_RTT_WR_RZQ_DIV2, /* 120-Ohm; RZQ = 240-Ohm */ 168 MV_DDR_RTT_WR_RZQ_DIV1, /* 240-Ohm; RZQ = 240-Ohm */ 169 MV_DDR_RTT_WR_HIZ, 170 MV_DDR_RTT_WR_RZQ_DIV3, /* 80-Ohm; RZQ = 240-Ohm */ 171 MV_DDR_RTT_WR_RZQ_LAST 172 }; 173 174 enum mv_ddr_dic_evalue { 175 MV_DDR_DIC_RZQ_DIV7, /* 34-Ohm; RZQ = 240-Ohm */ 176 MV_DDR_DIC_RZQ_DIV5, /* 48-Ohm; RZQ = 240-Ohm */ 177 MV_DDR_DIC_RZQ_LAST 178 }; 179 180 /* phy electrical configuration values */ 181 enum mv_ddr_ohm_evalue { 182 MV_DDR_OHM_30 = 30, 183 MV_DDR_OHM_48 = 48, 184 MV_DDR_OHM_60 = 60, 185 MV_DDR_OHM_80 = 80, 186 MV_DDR_OHM_120 = 120, 187 MV_DDR_OHM_240 = 240, 188 MV_DDR_OHM_LAST 189 }; 190 191 /* mac electrical configuration values */ 192 enum mv_ddr_odt_cfg_evalue { 193 MV_DDR_ODT_CFG_NORMAL, 194 MV_DDR_ODT_CFG_ALWAYS_ON, 195 MV_DDR_ODT_CFG_LAST 196 }; 197 198 enum mv_ddr_dev_width { /* sdram device width */ 199 MV_DDR_DEV_WIDTH_4BIT, 200 MV_DDR_DEV_WIDTH_8BIT, 201 MV_DDR_DEV_WIDTH_16BIT, 202 MV_DDR_DEV_WIDTH_32BIT, 203 MV_DDR_DEV_WIDTH_LAST 204 }; 205 206 enum mv_ddr_die_capacity { /* total sdram capacity per die, megabits */ 207 MV_DDR_DIE_CAP_256MBIT, 208 MV_DDR_DIE_CAP_512MBIT = 0, 209 MV_DDR_DIE_CAP_1GBIT, 210 MV_DDR_DIE_CAP_2GBIT, 211 MV_DDR_DIE_CAP_4GBIT, 212 MV_DDR_DIE_CAP_8GBIT, 213 MV_DDR_DIE_CAP_16GBIT, 214 MV_DDR_DIE_CAP_32GBIT, 215 MV_DDR_DIE_CAP_12GBIT, 216 MV_DDR_DIE_CAP_24GBIT, 217 MV_DDR_DIE_CAP_LAST 218 }; 219 220 enum mv_ddr_pkg_rank { /* number of package ranks per dimm */ 221 MV_DDR_PKG_RANK_1, 222 MV_DDR_PKG_RANK_2, 223 MV_DDR_PKG_RANK_3, 224 MV_DDR_PKG_RANK_4, 225 MV_DDR_PKG_RANK_5, 226 MV_DDR_PKG_RANK_6, 227 MV_DDR_PKG_RANK_7, 228 MV_DDR_PKG_RANK_8, 229 MV_DDR_PKG_RANK_LAST 230 }; 231 232 enum mv_ddr_pri_bus_width { /* number of primary bus width bits */ 233 MV_DDR_PRI_BUS_WIDTH_8, 234 MV_DDR_PRI_BUS_WIDTH_16, 235 MV_DDR_PRI_BUS_WIDTH_32, 236 MV_DDR_PRI_BUS_WIDTH_64, 237 MV_DDR_PRI_BUS_WIDTH_LAST 238 }; 239 240 enum mv_ddr_bus_width_ext { /* number of extension bus width bits */ 241 MV_DDR_BUS_WIDTH_EXT_0, 242 MV_DDR_BUS_WIDTH_EXT_8, 243 MV_DDR_BUS_WIDTH_EXT_LAST 244 }; 245 246 enum mv_ddr_die_count { 247 MV_DDR_DIE_CNT_1, 248 MV_DDR_DIE_CNT_2, 249 MV_DDR_DIE_CNT_3, 250 MV_DDR_DIE_CNT_4, 251 MV_DDR_DIE_CNT_5, 252 MV_DDR_DIE_CNT_6, 253 MV_DDR_DIE_CNT_7, 254 MV_DDR_DIE_CNT_8, 255 MV_DDR_DIE_CNT_LAST 256 }; 257 258 #define IS_ACTIVE(mask, id) \ 259 ((mask) & (1 << (id))) 260 261 #define VALIDATE_ACTIVE(mask, id) \ 262 { \ 263 if (IS_ACTIVE(mask, id) == 0) \ 264 continue; \ 265 } 266 267 #define IS_IF_ACTIVE(if_mask, if_id) \ 268 ((if_mask) & (1 << (if_id))) 269 270 #define VALIDATE_IF_ACTIVE(mask, id) \ 271 { \ 272 if (IS_IF_ACTIVE(mask, id) == 0) \ 273 continue; \ 274 } 275 276 #define IS_BUS_ACTIVE(if_mask , if_id) \ 277 (((if_mask) >> (if_id)) & 1) 278 279 #define VALIDATE_BUS_ACTIVE(mask, id) \ 280 { \ 281 if (IS_BUS_ACTIVE(mask, id) == 0) \ 282 continue; \ 283 } 284 285 #define DDR3_IS_ECC_PUP3_MODE(if_mask) \ 286 (((if_mask) == BUS_MASK_16BIT_ECC_PUP3) ? 1 : 0) 287 288 #define DDR3_IS_ECC_PUP4_MODE(if_mask) \ 289 (((if_mask) == BUS_MASK_32BIT_ECC || \ 290 (if_mask) == BUS_MASK_16BIT_ECC) ? 1 : 0) 291 292 #define DDR3_IS_16BIT_DRAM_MODE(mask) \ 293 (((mask) == BUS_MASK_16BIT || \ 294 (mask) == BUS_MASK_16BIT_ECC || \ 295 (mask) == BUS_MASK_16BIT_ECC_PUP3) ? 1 : 0) 296 297 #define DDR3_IS_ECC_PUP8_MODE(if_mask) \ 298 (((if_mask) == MV_DDR_32BIT_ECC_PUP8_BUS_MASK || \ 299 (if_mask) == MV_DDR_64BIT_ECC_PUP8_BUS_MASK) ? 1 : 0) 300 301 #define MV_DDR_IS_64BIT_DRAM_MODE(mask) \ 302 ((((mask) & MV_DDR_64BIT_BUS_MASK) == MV_DDR_64BIT_BUS_MASK) || \ 303 (((mask) & MV_DDR_64BIT_ECC_PUP8_BUS_MASK) == MV_DDR_64BIT_ECC_PUP8_BUS_MASK) ? 1 : 0) 304 305 #define MV_DDR_IS_32BIT_IN_64BIT_DRAM_MODE(mask, sphys) \ 306 (((sphys) == 9) && \ 307 (((mask) == BUS_MASK_32BIT) || \ 308 ((mask) == MV_DDR_32BIT_ECC_PUP8_BUS_MASK)) ? 1 : 0) 309 310 #define MV_DDR_IS_HALF_BUS_DRAM_MODE(mask, sphys) \ 311 (MV_DDR_IS_32BIT_IN_64BIT_DRAM_MODE(mask, sphys) || \ 312 DDR3_IS_16BIT_DRAM_MODE(mask)) 313 314 struct mv_ddr_topology_map *mv_ddr_topology_map_get(void); 315 unsigned int mv_ddr_cl_calc(unsigned int taa_min, unsigned int tclk); 316 unsigned int mv_ddr_cwl_calc(unsigned int tclk); 317 int mv_ddr_topology_map_update(void); 318 unsigned short mv_ddr_bus_bit_mask_get(void); 319 unsigned int mv_ddr_if_bus_width_get(void); 320 unsigned int mv_ddr_cs_num_get(void); 321 int mv_ddr_is_ecc_ena(void); 322 unsigned long long mv_ddr_mem_sz_per_cs_get(void); 323 unsigned long long mv_ddr_mem_sz_get(void); 324 unsigned int mv_ddr_rtt_nom_get(void); 325 unsigned int mv_ddr_rtt_park_get(void); 326 unsigned int mv_ddr_rtt_wr_get(void); 327 unsigned int mv_ddr_dic_get(void); 328 329 #endif /* _MV_DDR_TOPOLOGY_H */ 330